Commit Graph

376296 Commits

Author SHA1 Message Date
Pavel Labath 4e0e79dd34 [lldb] Simplify some lldb-server tests
Remove manual test duplication.
2021-01-06 15:39:51 +01:00
KareemErgawy-TomTom f60e0a91fb [MLIR][SPIRV] Add `UnsignedOp` trait.
This commit adds a new trait that can be attached to ops that have
unsigned semantics.

TODO:
- Check if other places in code can use the new attribute (possibly in this patch).
- Add a similar `SignedOp` attribute (in a new patch).

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D94068
2021-01-06 15:28:41 +01:00
Simon Pilgrim 26c486c2eb [TableGen] RegisterBankEmitter - Pass Twine by const reference instead of by value. NFCI. 2021-01-06 14:22:05 +00:00
Simon Pilgrim df5c2caf0f [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI. 2021-01-06 14:22:04 +00:00
Simon Pilgrim 396dd6cd3d [ProfileData] Pass Twine by const reference instead of by value.
Its only used by DiagnosticInfoSampleProfile which takes a const reference anyhow.
2021-01-06 14:22:03 +00:00
Sven van Haastregt 29d375f5ff [OpenCL][NFC] Improve OpenCL test file naming
Change "negative" into "invalid" and put "invalid" at the beginning of
the file name, following the bulk of the invalid tests in the
SemaOpenCL directory.

Use the "invalid-" prefix only for tests that contain only invalid
constructs.

Drop the "valid" suffix for CodeGen tests, as inputs in this directory
are supposed to be valid anyway.
2021-01-06 14:16:44 +00:00
Simon Pilgrim 37ac4f865f [Hexagon] Regenerate zext-v4i1.ll tests
This will be improved by part of the work for D86578
2021-01-06 12:56:06 +00:00
Jan Svoboda ce8c59e6af Reapply multiple "[clang][cli]" patches
This reverts 7ad666798f and 1876a2914f that reverted:

741978d727 [clang][cli] Port CodeGen option flags to new option parsing system
383778e217 [clang][cli] Port LangOpts option flags to new option parsing system
aec2991d08 [clang][cli] Port LangOpts simple string based options to new option parsing system
95d3cc67ca [clang][cli] Port CodeGenOpts simple string flags to new option parsing system
27b7d64688 [clang][cli] Streamline MarshallingInfoFlag description
70410a2649 [clang][cli] Let denormalizer decide how to render the option based on the option class
63a24816f5 [clang][cli] Implement `getAllArgValues` marshalling

Commit 741978d727 accidentally changed the `Group` attribute of `g[no_]column_info` options from `g_flags_Group` to `g_Group`, which changed the debug info options passed to cc1 by the driver.

Similar change was also present in 383778e217, which accidentally added `Group<f_Group>` to `f[no_]const_strings` and `f[no_]signed_wchar`.

This patch corrects all three accidental changes by replacing `Bool{G,F}Option` with `BoolCC1Option`.
2021-01-06 13:27:19 +01:00
Tomas Matheson 643e3c9076 [AArch64] Add BRB IALL and BRB INJ instructions
BRB IALL: Invalidate the Branch Record Buffer
BRB INJ: Branch Record Injection into the Branch Record Buffer

Parser changes based on work by Simon Tatham.

These are two-word mnemonics. The assembly parser works by special-casing
the mnemonic in order to parse the second word as a plain identifier token.

Reviewed by: MarkMurrayARM

Differential Revision: https://reviews.llvm.org/D93899
2021-01-06 12:10:22 +00:00
Guillaume Chatelet aa9db51ef6 [libc] Align src buffer instead of dst buffer
We used to align destination buffer instead of source buffer for the loop of block copy.
This is a mistake.

Differential Revision: https://reviews.llvm.org/D93457
2021-01-06 12:04:53 +00:00
Guillaume Chatelet 223a6f94c5 [libc] remove modulo from CircularArrayRef iterator 2021-01-06 12:03:52 +00:00
Simon Pilgrim dfcb872c3e [X86] Add scalar/vector test coverage for D93599
This expands the test coverage beyond just the boolvector/movmsk concat pattern
2021-01-06 11:58:27 +00:00
Stefan Pintilie cb0c034edc [PowerPC] Fix issue where vsrq is given incorrect shift vector
The new Power10 instruction vsrq was being given the wrong shift vector.
The original code assumed that the shift would be found in bits 121 to 127.
This is not correct. The shift is found in bits 57 to 63.
This can be fixed by swaping the first and second double words.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D94113
2021-01-06 05:56:09 -06:00
Florian Hahn 816dba48af
[VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC).
This patch updates VPWidenIntOrFpInductionRecipe to hold the start value
for the induction variable. This makes the start value explicit and
allows for adjusting the start value for a VPlan.

The flexibility will be used in further patches.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92129
2021-01-06 11:47:33 +00:00
Sander de Smalen aa280c99f7 [AArch64][SVE] Emit DWARF location expr for SVE (dbg.declare)
When using dbg.declare, the debug-info is generated from a list of
locals rather than through DBG_VALUE instructions in the MIR.
This patch is different from D90020 because it emits the DWARF
location expressions from that list of locals directly.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90044
2021-01-06 11:45:05 +00:00
Fraser Cormack 6e6e24bb09 [ValueTypes] Fix formatting on scalable vector warning (NFC) 2021-01-06 11:27:44 +00:00
Sander de Smalen 84a1120943 [LiveDebugValues] Handle spill locations with a fixed and scalable component.
This patch fixes the two LiveDebugValues implementations
(InstrRef/VarLoc)Based to handle cases where the StackOffset contains
both a fixed and scalable component.

This depends on the `TargetRegisterInfo::prependOffsetExpression` being
added in D90020. Feel free to leave comments on that patch if you have them.

Reviewed By: djtodoro, jmorse

Differential Revision: https://reviews.llvm.org/D90046
2021-01-06 11:30:13 +00:00
David Green 63dce70b79 [ARM] Handle any extend whilst lowering addw/addl/subw/subl
Same as a9b6440edd, use zanyext to treat any_extends as zero extends
during lowering to create addw/addl/subw/subl nodes.

Differential Revision: https://reviews.llvm.org/D93835
2021-01-06 11:26:39 +00:00
Florian Hahn 0ce5f402e0
[VPlan] Add getLiveInIRValue accessor to VPValue.
This patch adds a new getLiveInIRValue accessor to VPValue, which
returns the underlying value, if the VPValue is defined outside of
VPlan. This is required to handle scalars in VPTransformState, which
requires dealing with scalars defined outside of VPlan.

We can simply check VPValue::Def to determine if the value is defined
inside a VPlan.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92281
2021-01-06 11:20:42 +00:00
Alex Zinenko 74438eff51 [mlir] Use thread_local stack in LLVM dialect type parsing and printing
LLVM dialect type parsing and printing have been using a local stack object
forwarded between recursive functions responsible for parsing or printing
specific types. This stack is necessary to intercept (mutually) recursive
structure types and avoid inifinite recursion. This approach works only thanks
to the closedness of the LLVM dialect type system: types that don't belong to
the dialect are not allowed. Switch the approach to using a `thread_local`
stack inside the functions parsing the structure types. This makes the code
slightly cleaner by avoiding the need to pass the stack object around and, more
importantly, makes it possible to reconsider the closedness of the LLVM dialect
type system. As a nice side effect of this change, container LLVM dialect types
now support type aliases in their body (although it is currently impossible to
also use the alises when printing).

Depends On D93713

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93714
2021-01-06 12:05:24 +01:00
Ben Shi 351a45ca73 [RISCV][NFC] Add new test cases for mul 2021-01-06 18:55:56 +08:00
David Green ddb82fc76c [ARM] Handle any extend whilst lowering mull
Similar to 78d8a821e2 but for ARM, this handles any_extend whilst
creating MULL nodes, treating them as zextends.

Differential Revision: https://reviews.llvm.org/D93834
2021-01-06 10:51:12 +00:00
Florian Hahn f73c09caa2
[VPlan] Use public VPValue constructor in VPPRedInstPHIRecipe (NFC).
VPPredInstPHIRecipe does not need access to VPValue via friendship. It
can just use the public constructor,

Discussed as part of D92281.
2021-01-06 10:47:09 +00:00
Sander de Smalen e4cda13d5a Fix test failure in a7e3339f3b
Set the target-triple to aarch64 in debug-info-sve-dbg-value.mir
to avoid "'+sve' is not a recognized feature for this target"
diagnostic.
2021-01-06 10:43:48 +00:00
Andrzej Warzynski fa1e543e0b [flang][driver] Update error messages (nfc)
As per Flang's coding guidelines
(flang/docs/C++style.md#error-messages):
```
Messages should start with a capital letter.
```

This patch updates error messages in the driver (new and old) so that
they conform with the guideline above.

This change was suggested in one of the recent reviews:
https://reviews.llvm.org/D93712. It felt like this deserved a dedicated
patch, so sending it separately.
2021-01-06 10:41:27 +00:00
David Green a9b6440edd [AArch64] Handle any extend whilst lowering addw/addl/subw/subl
This adds an extra tablegen PatFrag, zanyext, which matches either any
extend or zext and uses that in the aarch64 backend to handle any
extends in addw/addl/subw/subl patterns.

Differential Revision: https://reviews.llvm.org/D93833
2021-01-06 10:35:23 +00:00
Oliver Stannard 4839378ca0 Revert "[sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature detection and support musl"
This reverts commit b7718b6175, because it
is causing build failures on all 32-bit ARM bots which build
compiler-rt.
2021-01-06 10:31:59 +00:00
Andrzej Warzynski e49dc2981c [flang][driver] Add checks for errors from `Prescan` and `Parse`
If either `Prescan` or `Parse` generate any fatal errors, the new driver
will:
  * report it (i.e. issue an error diagnostic)
  * exit early
  * return non-zero exit code
This behaviour is consistent with f18 (i.e. the old driver).

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93712
2021-01-06 10:19:44 +00:00
David Green 78d8a821e2 [AArch64] Handle any extend whilst lowering mull
Demanded bits may turn a sext or zext into an anyext if the top bits are
not needed. This currently prevents the lowering to instructions like
mull, addl and addw. This patch fixes the mull generation by keeping it
simple and treating them like zextends.

Differential Revision: https://reviews.llvm.org/D93832
2021-01-06 10:08:43 +00:00
Sander de Smalen a7e3339f3b [AArch64][SVE] Emit DWARF location expression for SVE stack objects.
Extend PEI to emit a DWARF expression for StackOffsets that have
a fixed and scalable component. This means the expression that needs
to be added is either:
  <base> + offset
or:
  <base> + offset + scalable_offset * scalereg

where for SVE, the scale reg is the Vector Granule Dwarf register, which
encodes the number of 64bit 'granules' in an SVE vector and which
the debugger can evaluate at runtime.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90020
2021-01-06 09:40:53 +00:00
Sander de Smalen a9f5e4375b [AArch64] Use faddp to implement fadd reductions.
Custom-expand legal VECREDUCE_FADD SDNodes
to benefit from pair-wise faddp instructions.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D59259
2021-01-06 09:36:51 +00:00
Sam Clegg 30d314aae1 [MC][WebAssembly] Avoid recalculating indexes in -gsplit-dwarf mode
Be consistent about asserting before setting WasmIndices.  Adding
these assertions revealed that we were duplicating a lot of work
and setting these indexed twice when running in DWO mode.

Differential Revision: https://reviews.llvm.org/D93650
2021-01-06 01:35:06 -08:00
Fraser Cormack e130dea92a [RISCV] Add vector integer mul/mulh/div/rem ISel patterns
There is no test coverage for the mulhs or mulhu patterns as I can't get
the DAGCombiner to generate them for scalable vectors. There are a few
places in that still need updating for that to work. I left the patterns
in regardless as they are correct.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94073
2021-01-06 09:24:07 +00:00
Aleksandr Platonov 979228f120 [clangd][fuzzyFind] Do not show stale symbols in the result.
This is follow up to D93393.
Without this patch `MergedIndex::fuzzyFind()` returns stale symbols from the static index even if these symbols were removed.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D93796
2021-01-06 11:17:12 +03:00
Pushpinder Singh 4909cb1a0f [OpenMP][AMDGPU] Use AMDGPU_KERNEL calling convention for entry function
AMDGPU backend requires entry functions/kernels to have AMDGPU_KERNEL
calling convention for proper linking.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D94060
2021-01-06 02:03:30 -05:00
Siva Chandra Reddy 7f7b0dc4e1 [libc] Add implementations of nextafter[f|l] functions.
A differential fuzzer for these functions has also been added.
Along the way, a small correction has been done to the normal/subnormal
limits of x86 long double values.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D94109
2021-01-05 22:32:39 -08:00
Siva Chandra Reddy 993d8ac5cb [libc] Add implementations of nearbyint[f|l].
The implementation is exactly the same as rint* as even rint does not
raise any floating point exceptions currently. [Note that the standards
do not specify that floating point exceptions must be raised - they
leave it up to the implementation to choose to raise FE_INEXACT when
rounding non-integral values.]

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D94112
2021-01-05 21:51:10 -08:00
Kazu Hirata cd088ba7e6 [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-05 21:15:59 -08:00
Kazu Hirata cea1c63756 [MachineSink] Construct SmallVector with iterator ranges (NFC) 2021-01-05 21:15:57 -08:00
Kazu Hirata 441650d589 [tools] Use llvm::append_range (NFC) 2021-01-05 21:15:56 -08:00
Christudasan Devadasan d68458bd56 [GlobalISel] Base implementation for sret demotion.
If the return values can't be lowered to registers
SelectionDAG performs the sret demotion. This patch
contains the basic implementation for the same in
the GlobalISel pipeline.

Furthermore, targets should bring relevant changes
during lowerFormalArguments, lowerReturn and
lowerCall to make use of this feature.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92953
2021-01-06 10:30:50 +05:30
Mircea Trofin c1cd42d698 [NFC] Removed unused prefixes in CodeGen/AMDGPU
This covers the tests starting with h-k.

Differential Revision: https://reviews.llvm.org/D94147
2021-01-05 20:22:40 -08:00
Yang Fan a032a4e799
[-Wcalled-once-parameter][NFC] Fix operator precedence warning 2021-01-06 12:16:30 +08:00
Peter Collingbourne 6dc3c117a3 scudo: Update a comment to match the Linux kernel behavior. NFCI. 2021-01-05 19:51:47 -08:00
Peter Collingbourne aed84542d5 ELF: Teach the linker about the 'B' augmentation string character.
This character indicates that when return pointer authentication is
being used, the function signs the return address using the B key.

Differential Revision: https://reviews.llvm.org/D93954
2021-01-05 19:51:11 -08:00
Mircea Trofin cdfd4c5c1a [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
More patches to follow. This covers the pertinent tests starting with e,
f, and g.

Differential Revision: https://reviews.llvm.org/D94124
2021-01-05 19:18:30 -08:00
Andrew Young 91f17ba24e
[mlir] Print the correct tool name in mlirTranslateMain
The passed in tool name is not used, causing the wrong tool name to be printed by the help text.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94120
2021-01-05 19:17:01 -08:00
Juneyoung Lee 29f8628d1f [Constant] Add containsPoisonElement
This patch

- Adds containsPoisonElement that checks existence of poison in constant vector elements,
- Renames containsUndefElement to containsUndefOrPoisonElement to clarify its behavior & updates its uses properly

With this patch, isGuaranteedNotToBeUndefOrPoison's tests w.r.t constant vectors are added because its analysis is improved.

Thanks!

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94053
2021-01-06 12:10:33 +09:00
Juneyoung Lee 8444a2494d [X86] Update X86InstCombineIntrinsic to use CreateShuffleVector with one vector
This patch updates X86InstCombineIntrinsic.cpp to use the newly updated CreateShuffleVector.

The tests are updated because the updated CreateShuffleVector uses poison value for the second vector.
If I didn't miss something, the masks in the tests are choosing elements from the first vector only; therefore the tests are having equivalent behavior.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D94059
2021-01-06 11:42:45 +09:00
Juneyoung Lee 4a8e6ed2f7 [SLP,LV] Use poison constant vector for shufflevector/initial insertelement
This patch makes SLP and LV emit operations with initial vectors set to poison constant instead of undef.
This is a part of efforts for using poison vector instead of undef to represent "doesn't care" vector.
The goal is to make nice shufflevector optimizations valid that is currently incorrect due to the tricky interaction between undef and poison (see https://bugs.llvm.org/show_bug.cgi?id=44185 ).

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D94061
2021-01-06 11:22:50 +09:00