3ceac21d37
Add OperandTypes for Thumb branch targets.
...
llvm-svn: 135199
2011-07-14 21:47:24 +00:00
651b230ca0
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
...
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
31756c2283
Range checking for CDP[2] immediates.
...
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
adb29b6dbb
Fix predicates for Thumb co-processor instructions.
...
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
39c67b5e08
Mark tBRIND as predicable.
...
llvm-svn: 134758
2011-07-08 22:33:49 +00:00
59a3ab6e46
Pseudo-ize tBRIND.
...
llvm-svn: 134755
2011-07-08 22:25:23 +00:00
7471937ad7
Make tBX_RET and tBX_RET_vararg predicable.
...
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.
llvm-svn: 134746
2011-07-08 21:50:04 +00:00
d61ae786bd
Pseudo-ize tBX_RET and tBX_RET_vararg.
...
llvm-svn: 134739
2011-07-08 21:10:35 +00:00
cb1b0b7130
Shuffle productions around a bit.
...
No functional change.
llvm-svn: 134737
2011-07-08 21:04:05 +00:00
204c128f66
Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
...
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
4af8647e17
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
...
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
166cd88645
Move Thumb tail call pseudos to Thumb.td file.
...
Fix a FIXME.
llvm-svn: 134727
2011-07-08 20:13:35 +00:00
95dee40343
Use TableGen'erated pseudo lowering for ARM.
...
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
llvm-svn: 134705
2011-07-08 17:40:42 +00:00
4def704a21
Pseudo-ize t2MOVCC[ri].
...
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
llvm-svn: 134242
2011-07-01 17:14:11 +00:00
e9cc901814
Refact ARM Thumb1 tMOVr instruction family.
...
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
llvm-svn: 134204
2011-06-30 23:38:17 +00:00
b98ab91e39
Thumb1 register to register MOV instruction is predicable.
...
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
llvm-svn: 134197
2011-06-30 22:10:46 +00:00
e4750ef6ec
Pseudo-ize the Thumb tTPsoft instruction.
...
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.
llvm-svn: 134178
2011-06-30 19:38:01 +00:00
417671a7b1
Pseudo-ize the Thumb tPOP_RET instruction.
...
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.
llvm-svn: 134172
2011-06-30 17:34:04 +00:00
d86f34d631
Refactor away tSpill and tRestore pseudos in ARM backend.
...
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.
llvm-svn: 134092
2011-06-29 20:26:39 +00:00
a6f7a1efcc
ARM Assembly support for Thumb mov-immediate.
...
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
llvm-svn: 133966
2011-06-27 23:54:06 +00:00
4c0bd9629d
Teach dag combine to match halfword byteswap patterns.
...
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
=> (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
=> (rotl (bswap x) 16)
This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.
rdar://9609108
llvm-svn: 133503
2011-06-21 06:01:08 +00:00
7ef7ddd2df
Clean up a few 80 column violations.
...
llvm-svn: 132946
2011-06-13 22:54:22 +00:00
410172bf5e
Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
...
rdar://problem/9556069
llvm-svn: 132699
2011-06-07 00:08:49 +00:00
9b67db8ea7
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
...
followed by a conditional and imm8.
llvm-svn: 132179
2011-05-27 03:50:53 +00:00
26ddb12118
Mark tBX as an indirect branch rather than a return.
...
llvm-svn: 132107
2011-05-26 03:41:12 +00:00
a946f476d3
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
...
llvm-svn: 132086
2011-05-25 21:53:50 +00:00
6b66ee1865
Move some code to a more logical place.
...
llvm-svn: 132043
2011-05-25 04:45:29 +00:00
310b3472ec
Change the order of tBX's operands so that the predicate operands come after the
...
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
llvm-svn: 132041
2011-05-25 04:45:23 +00:00
012247e60c
Rename tBX_Rm to tBX.
...
llvm-svn: 132040
2011-05-25 04:45:20 +00:00
deaf994ff0
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
...
reflect their actual meaning and match the ARM instructions.
llvm-svn: 132039
2011-05-25 04:45:14 +00:00
b745623b71
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
...
llvm-svn: 131189
2011-05-11 17:00:48 +00:00
f8be385c9b
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
...
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
llvm-svn: 130801
2011-05-03 22:31:24 +00:00
86c6e7057d
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
...
it's possible.
llvm-svn: 130764
2011-05-03 17:29:29 +00:00
168c9005b5
Add a few ARM coprocessor intrinsics. Testcases included
...
llvm-svn: 130763
2011-05-03 17:29:22 +00:00
a98cd22d96
Let the immediate leaf pattern take transforms and switch the signed
...
immediate patterns in arm to using the pattern.
Handles rdar://9299434
llvm-svn: 130386
2011-04-28 05:49:04 +00:00
57c892860e
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
...
print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
44887f9c7e
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
...
llvm-svn: 129548
2011-04-14 23:27:44 +00:00
dc8bf9ec08
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
f922b20922
Change MRC and MRC2 instructions to model the output register properly
...
llvm-svn: 128085
2011-03-22 15:06:24 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
d8f9b37f31
Add cdp/cdp2 instructions for thumb/thumb2
...
llvm-svn: 123929
2011-01-20 18:32:09 +00:00
cf99dc7eb9
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
...
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
cdcc4fc048
Fix a copy-pasto. When the tBR_JTr instruction was converted to using the
...
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
llvm-svn: 122303
2010-12-21 01:57:15 +00:00
b5743b9d76
Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
...
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
f5b17c32d2
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
bfef309d11
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
6217ecd634
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
1171e9e81d
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
5ab38b59e6
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
b0fa127f60
Fix encoding of Thumb1 LDRB and STRB.
...
llvm-svn: 121581
2010-12-10 22:11:13 +00:00
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
...
llvm-svn: 121496
2010-12-10 18:21:33 +00:00
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
62b68112da
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
529c7e8d1f
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
8a6449c46e
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
49bcd6ff85
Binary encoding for ARM tLDRspi and tSTRspi.
...
llvm-svn: 121186
2010-12-07 21:50:47 +00:00
327cf8ee5f
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
...
possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
6e517d658e
Encode the literal field for tCMPzi instruction.
...
llvm-svn: 121153
2010-12-07 17:48:24 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
ce18d7ebb5
Encode condition code for Thumb1 conditional branch instruction.
...
llvm-svn: 120865
2010-12-04 00:20:40 +00:00
127d7485f1
Use correct variable names to match the patterns.
...
llvm-svn: 120857
2010-12-03 23:44:24 +00:00
a09cbbeef5
Match pattern operand names to expected encoding field names. This corrects the
...
operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
e4fee20498
Remove incorrect BL target encoding (it's similar to, but not the same as the
...
ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
f799579ddd
No need to declare EncoderMethod property anymore; just assign to it.
...
llvm-svn: 120831
2010-12-03 19:31:00 +00:00
6423c29e14
Add FIXMEs.
...
llvm-svn: 120824
2010-12-03 18:37:17 +00:00
36110d5d1a
Don't overwrite the opcode passed into the T1Special pattern.
...
llvm-svn: 120782
2010-12-03 02:02:58 +00:00
4d8ff86b9e
Add Thumb encoding for some more instructions.
...
llvm-svn: 120780
2010-12-03 01:55:47 +00:00
9c25894995
Formatting. It's all the rage!
...
llvm-svn: 120533
2010-12-01 02:36:55 +00:00
8ed14ae48a
More refactoring. This time the T1pI pattern.
...
llvm-svn: 120532
2010-12-01 02:28:08 +00:00
c25545a1a7
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
7c646b924b
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
490240a5d9
Refactor T1sI and T1sIt encodings into helper classes.
...
llvm-svn: 120518
2010-12-01 01:20:15 +00:00
4915f56669
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
...
statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
811c936ed5
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
...
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
ddce9f3757
Minor cleanups. No functional change.
...
llvm-svn: 120372
2010-11-30 00:50:22 +00:00
62718de2b9
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
...
able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
85a8a72d85
Add some encoding for the adr instruction. Labels still need to be finished.
...
llvm-svn: 120365
2010-11-30 00:18:30 +00:00
ce3d6ca564
Predicate encoding should be withing {}s. And general cleanup.
...
llvm-svn: 120361
2010-11-30 00:08:20 +00:00
795f211418
Predicate encoding should be withing {}s.
...
llvm-svn: 120360
2010-11-30 00:05:25 +00:00
9a133f623c
Mark Darwin call instructions as using "r7" to prevent the frame-register
...
assignment instructions from being moved below / above calls.
rdar://8690640
llvm-svn: 120339
2010-11-29 22:43:27 +00:00
ee7c5659d7
Thumb encodings for conditional moves.
...
llvm-svn: 120334
2010-11-29 22:37:46 +00:00
5da8cae9ec
Refactor some of the "disassembly-only" instructions into a base class. This
...
reduces some code duplication.
llvm-svn: 120326
2010-11-29 22:15:03 +00:00
58bc36a3a9
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
232e52cfb7
Add more Thumb encodings.
...
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
ccba1a8d95
More Thumb encodings.
...
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
9600e97c60
Add Thumb encodings for REV instructions.
...
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
775899eb2e
Add more Thumb encodings.
...
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
22db31305f
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
3acd02706a
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
c31de25137
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
284326bd69
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
fe1de03629
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
e60fd5a9db
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
1825cc74f4
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
a82fb71324
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
c92a5770df
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
49a2e2384b
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
945b776b6e
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
...
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
...
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
9430eb489c
Comment out the defms until they're activated.
...
llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
...
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
...
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
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future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
fddf36d254
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
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codegen using the patterns; the latter gates the assembler recognizing the
instruction.
llvm-svn: 117931
2010-11-01 17:08:58 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
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various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
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and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
33fc3e095b
reapply r117858 with apparent editor malfunction fixed (somehow I
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got a dulicated line).
llvm-svn: 117860
2010-10-31 19:10:56 +00:00
e59eef3dd1
revert r117858 while I check out a failure I missed.
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llvm-svn: 117859
2010-10-31 19:05:32 +00:00
9293008e90
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
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Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
llvm-svn: 117858
2010-10-31 18:48:12 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
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llvm-svn: 115845
2010-10-06 21:36:43 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
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allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
fae8305e2b
Nuke the rest of the :comment references
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llvm-svn: 115373
2010-10-01 23:21:38 +00:00
c8e2e9d830
Nuke a few more unused asm strings
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llvm-svn: 115193
2010-09-30 19:53:58 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
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llvm-svn: 115160
2010-09-30 16:56:53 +00:00
4a9cb8f10e
Go ahead and jump!
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Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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llvm-svn: 115010
2010-09-29 00:49:25 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
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llvm-svn: 114703
2010-09-23 22:57:01 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
22f6922505
set isCompare for another three Thumb1 instructions
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llvm-svn: 113867
2010-09-14 22:00:50 +00:00
2afac8e9bd
set comparable for a bunch of Thumb instructions
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llvm-svn: 113849
2010-09-14 20:47:43 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
9877af3b46
grammar tweak
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llvm-svn: 113289
2010-09-07 21:30:25 +00:00
fef37287a8
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
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help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
llvm-svn: 112503
2010-08-30 19:49:58 +00:00
fa16acae44
Delete some unused instructions.
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llvm-svn: 110710
2010-08-10 19:36:22 +00:00
b128824b60
Move newlines before inline jumptables from the asm strings in .td files to
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the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
llvm-svn: 109948
2010-07-31 06:28:10 +00:00
523e554afa
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
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being moved around away from the jump table it references. rdar://8104340
llvm-svn: 106483
2010-06-21 21:27:27 +00:00
84511e1526
Clean up 80 column violations. No functional change.
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llvm-svn: 105350
2010-06-02 21:53:11 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
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llvm-svn: 104974
2010-05-28 17:51:20 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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llvm-svn: 104967
2010-05-28 17:37:40 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
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an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
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llvm-svn: 104661
2010-05-26 01:22:21 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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llvm-svn: 104115
2010-05-19 07:28:01 +00:00
Benjamin Kramer