9a19c240c0
AMDGPU: Materialize sign bits with bfrev
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If a constant is the same as the reverse of an inline immediate,
this is 4 bytes smaller than having to embed a 32-bit literal.
llvm-svn: 263201
2016-03-11 07:42:49 +00:00
8226fc4829
AMDGPU: Simplify boolean conditional return statements
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Patch by Richard Thomson
llvm-svn: 262536
2016-03-02 23:00:21 +00:00
cc4c8718ed
[AMDGPU] Rename $dst operand to $vdst for VOP instructions.
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Summary: This change renames output operand for VOP instructions from dst to vdst. This is needed to enable decoding named operands for disassembler.
Reviewers: vpykhtin, tstellarAMD, arsenm
Subscribers: arsenm, llvm-commits, nhaustov
Projects: #llvm-amdgpu-spb
Differential Revision: http://reviews.llvm.org/D16920
llvm-svn: 260986
2016-02-16 18:14:56 +00:00
3add6439d0
AMDGPU: Add MachineInstr overloads for instruction format tests
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llvm-svn: 250797
2015-10-20 04:35:43 +00:00
e0b44040aa
AMDGPU: Simplify debug printing
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llvm-svn: 247345
2015-09-10 21:51:19 +00:00
4635915504
AMDGPU/SI: Remove VCCReg
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llvm-svn: 244380
2015-08-08 00:41:48 +00:00
6942d1a034
AMDGPU/SI: Remove source uses of VCCReg
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llvm-svn: 244379
2015-08-08 00:41:45 +00:00
e48fe2a27a
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
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Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11061
llvm-svn: 242146
2015-07-14 14:15:03 +00:00
db5a11f698
AMDGPU/SI: Select mad patterns to v_mac_f32
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The two-address instruction pass will convert these back to v_mad_f32
if necessary.
Differential Revision: http://reviews.llvm.org/D11060
llvm-svn: 242038
2015-07-13 15:47:57 +00:00
ab6e9c0f94
AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
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This is convered by existing testcases and will be exposed by a future
commit.
llvm-svn: 241817
2015-07-09 16:30:36 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Matt Arsenault