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5 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin a6322941ff [AMDGPU] gfx1010 VMEM and SMEM implementation 
Differential Revision: https://reviews.llvm.org/D61330

llvm-svn: 359621
 2019-04-30 22:08:23 +00:00
Puyan Lotfi 43e94b15ea Followup on Proposal to move MIR physical register namespace to '$' sigil. 
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
 2018-01-31 22:04:26 +00:00
Alexander Timofeev 28da06778f [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one 
Differential revision: https://reviews.llvm.org/D38754

llvm-svn: 317884
 2017-11-10 12:21:10 +00:00
Alexander Timofeev 9dff31c769 [AMDGPU] : revert r315908 
llvm-svn: 315916
 2017-10-16 16:57:37 +00:00
Alexander Timofeev 3828242c7e [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one 
Differential revision: https://reviews.llvm.org/D38754

llvm-svn: 315908
 2017-10-16 14:35:29 +00:00