Commit Graph

18512 Commits

Author SHA1 Message Date
Owen Anderson 7bc3b11a56 Fix broken encoding of tCBNZ.
llvm-svn: 136837
2011-08-03 23:21:48 +00:00
Eli Friedman 30a49e93e3 New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Benjamin Kramer 103e2ec2df Remove unused variables.
llvm-svn: 136803
2011-08-03 19:53:48 +00:00
Jakob Stoklund Olesen da618420ee Handle IMPLICIT_DEF instructions in X86FloatingPoint.
This fixes PR10575.

llvm-svn: 136787
2011-08-03 16:33:19 +00:00
Eli Friedman 5c863aeefd ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.
llvm-svn: 136737
2011-08-02 22:44:16 +00:00
Eli Friedman 04c5025cd5 Don't create a ridiculous EXTRACT_ELEMENT. PR10563.
The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.

llvm-svn: 136711
2011-08-02 18:38:35 +00:00
Owen Anderson 713406f88d Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
Jim Grosbach c8c63914c5 Tidy up. 80 columns.
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Bruno Cardoso Lopes 5ada908140 Make this kind of lowering to be supported by 256-bit instructions:
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

llvm-svn: 136691
2011-08-02 16:06:18 +00:00
Roman Divacky e6a11dcc72 Remove trailing semicolon.
llvm-svn: 136690
2011-08-02 15:54:03 +00:00
Roman Divacky 038c1a1a73 Sketch out PowerPC ELF writer. This is enough to get clang -integrated-as
to compile a working hello world on FreeBSD/PPC32.

llvm-svn: 136689
2011-08-02 15:51:38 +00:00
Nick Lewycky a530a4d925 Bail from FastISel when we encounter a volatile memset intrinsic. Patch by Ivan
Krasin!

llvm-svn: 136663
2011-08-02 00:40:16 +00:00
Jim Grosbach 9f620a6883 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
Jim Grosbach 0f731b3232 Fix comments.
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
Bruno Cardoso Lopes a8e3673816 Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654
2011-08-01 21:54:09 +00:00
Bruno Cardoso Lopes 616fe60548 Teach PreprocessISelDAG to be aware of vector types and to not process them.
llvm-svn: 136653
2011-08-01 21:54:05 +00:00
Bruno Cardoso Lopes bd30a4b584 Lower CONCAT_VECTORS to use two VINSERTF128 instructions instead of
using a stack store.

llvm-svn: 136652
2011-08-01 21:54:02 +00:00
Chandler Carruth c099a6f9ce Actually finish switching to the new system for Target sublibrary
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

llvm-svn: 136643
2011-08-01 19:55:11 +00:00
Bruno Cardoso Lopes 7513939ddd Since vectors with all ones can't be created with a 256-bit instruction,
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

llvm-svn: 136642
2011-08-01 19:51:53 +00:00
Evan Cheng de4ae46607 Set endianess and pointer size for PPC Linux. Bug noticed by Roman Divacky.
llvm-svn: 136639
2011-08-01 19:43:05 +00:00
Richard Osborne 0cc000ef29 Fix crash with varargs function with no named parameters.
llvm-svn: 136623
2011-08-01 16:45:59 +00:00
Douglas Gregor d41f3a161f Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.
llvm-svn: 136621
2011-08-01 16:29:27 +00:00
Bill Wendling f891bf8b30 Add the 'resume' instruction for the new EH rewrite.
This adds the 'resume' instruction class, IR parsing, and bitcode reading and
writing. The 'resume' instruction resumes propagation of an existing (in-flight)
exception whose unwinding was interrupted with a 'landingpad' instruction (to be
added later).

llvm-svn: 136589
2011-07-31 06:30:59 +00:00
Chandler Carruth 27246dc784 Switch another of the old dependencies on implicitly produced synthetic
rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.

llvm-svn: 136567
2011-07-30 10:10:23 +00:00
Bill Wendling ad088e6724 Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.

llvm-svn: 136556
2011-07-30 05:42:50 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint.
Fixes rdar://9866494

llvm-svn: 136523
2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach 20d38124a2 ARM SRS and RFE instructions are not code-gen only.
llvm-svn: 136475
2011-07-29 17:51:39 +00:00
Jim Grosbach 3b764cfd48 ARM range checking for mode on CPS instruction.
llvm-svn: 136473
2011-07-29 17:42:17 +00:00
Jim Grosbach e658f4faeb Update FIXME.
llvm-svn: 136470
2011-07-29 17:36:04 +00:00
Jim Grosbach 47859c8ab0 Tweak comment.
llvm-svn: 136468
2011-07-29 17:33:29 +00:00
Eli Friedman adec587d5c Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to be
working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)

llvm-svn: 136457
2011-07-29 03:05:32 +00:00
Bruno Cardoso Lopes 65ce5ea3ba Fix two tests that I crashed in the previous commits. The mask elts
on the second half must be reindexed.

llvm-svn: 136454
2011-07-29 02:05:28 +00:00
Bruno Cardoso Lopes 81eb193f2e Match VPERMIL masks more strictly and update the target specific mask
generation to always catch the weird cases.

llvm-svn: 136453
2011-07-29 01:31:15 +00:00
Bruno Cardoso Lopes 795f558532 Add DecodeShuffle shuffle support for VPERMIPD variantes
llvm-svn: 136452
2011-07-29 01:31:11 +00:00
Bruno Cardoso Lopes d23709b18c Add v8i32 and v4i64 vpermil patterns
llvm-svn: 136451
2011-07-29 01:31:07 +00:00
Bruno Cardoso Lopes c00f6728bc Fix a bug while generating target specific VPERMIL masks: skip
undef mask elements. This fixes PR10529.

llvm-svn: 136450
2011-07-29 01:31:04 +00:00
Bruno Cardoso Lopes b9ba465de8 Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.
Also tidy up code a bit.

llvm-svn: 136449
2011-07-29 01:31:02 +00:00
Bruno Cardoso Lopes 6aee388423 Cleanup PALIGNR handling and remove the old palign pattern fragment.
Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

llvm-svn: 136448
2011-07-29 01:30:59 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand.
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
2011-07-29 00:27:32 +00:00
Chandler Carruth 9d7feab3e0 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Jim Grosbach dd475c39d7 PLD and PLI are not predicable in ARM mode.
llvm-svn: 136427
2011-07-28 23:22:41 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
2011-07-28 21:57:55 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
2011-07-28 21:34:26 +00:00
Jim Grosbach bfb439b140 Add fixme.
llvm-svn: 136375
2011-07-28 19:46:12 +00:00
Owen Anderson 7c965e7520 Update comments.
llvm-svn: 136367
2011-07-28 17:56:55 +00:00