Commit Graph

342157 Commits

Author SHA1 Message Date
Hanhan Wang 4687822b9e [mlir][Linalg] Add a roundtrip test for indexed_generic op with tensors.
Summary:
After D72555 has been landed, `linalg.indexed_generic` also accepts ranked
tensor as input and output. Add a test for it.

Differential Revision: https://reviews.llvm.org/D74267
2020-02-10 15:51:59 -05:00
Martin Storsjö bc8e442188 [test] Disable the Passes/PluginsTest cases on windows with BUILD_SHARED_LIBS
The plugin expects to have undefined references to symbols exported
by the loading process, which isn't supported by shared libraries
on windows.

Differential Revision: https://reviews.llvm.org/D74042
2020-02-10 22:50:36 +02:00
Nico Weber e4e9e106b9 git bisect docs: formatting tweaks 2020-02-10 15:47:59 -05:00
Xiangling Liao 660b0d7f7b [AIX] Enable frame pointer for AIX and add related test suite
This patch:
   - enable frame pointer for AIX;
   - update some of red zone comments;
   - add/update testcases;

Differential Revision: https://reviews.llvm.org/D72454
2020-02-10 15:43:41 -05:00
Matt Arsenault f270da6bfc RegisterCoalescer: Add LaneMask to debug printing 2020-02-10 12:34:33 -08:00
Nico Weber 8116635e8b add GitBisecting to toctrees to try and placate the sphinx bot 2020-02-10 15:33:28 -05:00
Sterling Augustine 0bd48c3d4e [DebugInfo] Support file-level include directories when generating DWARFv5 LineTable prologues.
Differential Revision: https://reviews.llvm.org/D74249
2020-02-10 12:24:46 -08:00
Nico Weber c1adb88a31 git bisect docs: try to make commit ascii art show up 2020-02-10 15:18:58 -05:00
Jan Korous efcf643000 Reland "[clangd][test] Disable a particular testcase in FindExplicitReferencesTest when LLVM_ENABLE_EXPENSIVE_CHECKS""
The test got re-enabled after d54d71b67e landed.

However it seems that the order is still not deterministic as it
currently passes with -DLLVM_ENABLE_EXPENSIVE_CHECKS=OFF but randomly
fails with expensive checks ON.
2020-02-10 12:17:02 -08:00
Sanjay Patel 0ad6e726ec [Transforms] add phase ordering tests for min/max/abs; NFC
Test that instcombine and early-cse can cooperate
to reduce sequences of select patterns that are not
composed of the same underlying instructions.

There's a bug in EarlyCSE (PR41083), and we can test
how much a possible fix (D74285) may affect optimization.
2020-02-10 15:14:46 -05:00
Vedant Kumar d23c15a687 Do not define AcceptPIDFromInferior when it will not be used 2020-02-10 12:06:46 -08:00
Nicolas Vasilache 8513ff05c8 [mlir][VectorOps][EDSC] Add EDSC for VectorOps
Summary:
This revision adds EDSC support for VectorOps to enable the creation of a `vector_matmul` declaratively. The `vector_matmul` is a simple configuration
 of the `vector.contract` op that follows the StructuredOps abstraction.

Differential Revision: https://reviews.llvm.org/D74284
2020-02-10 15:01:14 -05:00
Sanjay Patel 62ce7e650a [InstCombine] fix use check when canonicalizing abs/nabs
We were checking for extra uses of the negated operand even
if we were not going to create it as part of this canonicalization.

This was showing up as a regression when we limit EarlyCSE as
proposed in D74285.
2020-02-10 14:57:37 -05:00
Sanjay Patel 93073e52b1 [InstCombine] add tests for abs with extra use of operand; NFC 2020-02-10 14:57:37 -05:00
Alexey Bataev 04a830f80a [OPENMP50]Support for acquire clause.
Added full support for acquire clause in flush|atomic directives.
2020-02-10 14:51:46 -05:00
diggerlin aa86311e62 [AIX][XCOFF] Support Mergeable2ByteCString and Mergeable4ByteCString
SUMMARY:
The patch is enable to support Mergeable2ByteCString and Mergeable4ByteCString

Reviewers: daltenty
Subscribers: wuzish, nemanjai, hiraditya

Differential Revision: https://reviews.llvm.org/D74164
2020-02-10 14:45:54 -05:00
Ted Woodward 6fd818c5a9 Don't fail step out if remote server doesn't implement qMemoryRegionInfo
Summary:
The return address validation in D71372 will fail if the memory permissions can't be determined. Many embedded stubs either don't implement the qMemoryRegionInfo packet, or don't have memory permissions at all.

Remove the return from the if clause that calls GetLoadAddressPermissions, so this call failing doesn't cause the step out to abort. Instead, assume that the memory permission check doesn't apply to this type of target.

Reviewers: labath, jingham, clayborg, mossberg

Reviewed By: labath, jingham

Subscribers: lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D72513
2020-02-10 13:40:44 -06:00
Nico Weber 45c6c82e90 Add documentation on git bisecting across the MLIR merge
Differential Revision: https://reviews.llvm.org/D73988
2020-02-10 14:25:43 -05:00
serge-sans-paille 3185c30c54 Prefer __vector over vector keyword for altivec
`vector' uses the keyword-and-predefine mode from gcc, while __vector is
reliably supported.

As a side effect, it also makes the code consistent in its usage of __vector.

Differential Revision: https://reviews.llvm.org/D74129
2020-02-10 20:23:26 +01:00
David Goldman 6ff0228c6d [clang] Add `forceReload` clangd extension to 'textDocument/didChange'
Summary:
- This option forces a preamble rebuild to handle the odd case
  of a missing header file being added

Reviewers: sammccall

Subscribers: ilya-biryukov, javed.absar, MaskRay, jkorous, arphaman, jfb, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73916
2020-02-10 14:02:02 -05:00
Nico Weber b50431defb fix some typos to cycle bots 2020-02-10 13:51:23 -05:00
Eric Christopher 102814b4d3 Continue removing llgo. 2020-02-10 10:33:58 -08:00
Max Moroz 405093045f [compiler-rt] Follow up fix for the refactoring in https://reviews.llvm.org/D74137.
Summary:
The refactoring has caused a failure in
http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/29265

The idea of failing the symbolization when the symbolizer bufer is too small
was incorrect. The symbolizer can be invoked for other frames that may fit into
the buffer and get symbolized.

Reviewers: vitalybuka, eugenis

Subscribers: dberris, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D74343
2020-02-10 10:28:06 -08:00
Florian Hahn d15325c9e0 [ValueLattice] Remove obsolete getConstantInt (NFC).
ConstantInt values are always represented as constant ranges with a
single element. getConstantInt is obsolete, as pointed out by @nikic
during D60581.

Reviewers: nikic

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D74329
2020-02-10 18:25:21 +00:00
Stephen Neuendorffer 4468188db8 [MLIR] Fix lib/Dialect/Linalg/EDSC for BUILD_SHARED_LIBS=on 2020-02-10 10:23:56 -08:00
Stephen Neuendorffer 1eba3f326c [MLIR] Fix lib/ExecutionEngine for BUILD_SHARED_LIBS=on 2020-02-10 10:23:56 -08:00
Stephen Neuendorffer ed56633fb9 [MLIR][Standard] Implement constant folding for IndexCast
Differential Revision: https://reviews.llvm.org/D73672
2020-02-10 10:23:56 -08:00
Stephen Neuendorffer 12df427fb2 [MLIR][Standard] Add folding for indexCast(indexCast(x)) -> x
Allow this only if the types are the same.  e.g.:
i16 -> index -> i16  or
index -> i16 -> index

Differential Revision: https://reviews.llvm.org/D73671
2020-02-10 10:23:56 -08:00
Stephen Neuendorffer b80a9ca8cb [MLIR] Allow non-binary operations to be commutative
NFC for binary operations.

Differential Revision: https://reviews.llvm.org/D73670
2020-02-10 10:23:55 -08:00
Rachel Craik 1f55420065 [LoopCacheAnalysis]: Add support for negative stride
LoopCacheAnalysis currently assumes the loop will be iterated over in
a forward direction. This patch addresses the issue by using the
absolute value of the stride when iterating backwards.

Note: this patch will treat negative and positive array access the
same, resulting in the same cost being calculated for single and
bi-directional access patterns. This should be improved in a
subsequent patch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D73064
2020-02-10 13:22:35 -05:00
Dimitry Andric 92e267a94d [Sanitizers] Get link map on FreeBSD via documented API
Summary:
Instead of hand-crafting an offset into the structure returned by
dlopen(3) to get at the link map, use the documented API.  This is
described in dlinfo(3): by calling it with `RTLD_DI_LINKMAP`, the
dynamic linker ensures the right address is returned.

Reviewers: devnexen, emaste, MaskRay, krytarowski

Reviewed By: krytarowski

Subscribers: krytarowski, vitalybuka, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D73990
2020-02-10 19:21:19 +01:00
Vedant Kumar eaeb5610ce debugserver: Rely on mig architectures being specified externally
Look up the -arch flags to pass to the mig invocation from an
optionally-defined MIG_ARCHS variable. We can't use CMAKE_OSX_ARCHS
because the {i,tv,watch}OS builds don't use this mechanism to achieve
fat builds (they build each slice separately & then lipo them together).

This supercedes the mig -arch/-isysroot fix from
510758dae2.
2020-02-10 10:13:05 -08:00
Jonas Paulsson fcdb99e0b5 [SystemZ] Add a subtarget cache like some other targets already have.
Each function is with this compiled with the SystemZSubtarget initialized
from the functions attributes.

Review: Ulrich Weigand.

Differential Revision: https://reviews.llvm.org/D74086
2020-02-10 13:10:58 -05:00
Eric Christopher 372bfc65de Remove llgo per discussion on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139058.html

Approved by dblaikie, pcc.
2020-02-10 10:10:15 -08:00
Vedant Kumar 936d1427da [Host.mm] Check for the right macro instead of inlining it
Differential Revision: https://reviews.llvm.org/D73938
2020-02-10 10:06:40 -08:00
Matt Arsenault 7af7b96a9b AMDGPU: Move R600 test compatability hack
Instead of handling the r600 intrinsics on amdgcn, handle the amdgcn
intrinsics on r600.
2020-02-10 10:02:06 -08:00
Simon Pilgrim f319074824 [X86] combineConcatVectorOps - combine X86ISD::PACKSS ops 2020-02-10 17:48:02 +00:00
Simon Pilgrim 74c0f98cf5 [X86] combineConcatVectorOps - combine X86ISD::VPERMI ops 2020-02-10 17:48:01 +00:00
Michael Kruse 84c934a5cb Silence compiler warning. NFC.
The idiom

    for (auto i = n - n; i < n; i += 1)

was intended to automatically derive the type of i from n
(signed/unsigned int) and avoid the 'mixed signed/unsigned comparison'
warning. However, almost-always-auto was never used in the LLVM coding
style (although we used it in Polly for some time) and I did never
intended to use this idiom upstream.

PVS Studio may warns about this idiom as 'warning: both sides of
operator are equivalent [misc-redundant-expression]'.

Remove the use of auto and directly use unsigned.

Also see http://llvm.org/PR44768
2020-02-10 11:38:22 -06:00
aartbik 83003db430 [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect
Summary:
This allows for lowering of VectorOps (and others) into a LLVM IR
that maps directly to efficient implementations on the target machines.

http://llvm.org/docs/LangRef.html#experimental-vector-reduction-intrinsics

Reviewers: ftynse, andydavis1, nicolasvasilache, rriddle

Reviewed By: ftynse, rriddle

Subscribers: jfb, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74171
2020-02-10 09:19:05 -08:00
Nicolas Vasilache 75394e1301 [mlir][EDSC] Almost NFC - Refactor and untangle EDSC dependencies
This CL refactors EDSCs to layer them better and break unnecessary
dependencies. After this refactoring, the top-level EDSC target only
depends on IR but not on Dialects anymore and each dialect has its
own EDSC directory.

This simplifies the layering and breaks cyclic dependencies.
In particular, the declarative builder + folder are made explicit and
are now confined to Linalg.

As the refactoring occurred, certain classes and abstractions that were not
paying for themselves have been removed.

Differential Revision: https://reviews.llvm.org/D74302
2020-02-10 12:10:41 -05:00
Simon Pilgrim 2463b8c97d [X86] combineConcatVectorOps - combine VSHLI/VSRAI/VSRLI ops
Non-AVX512BW targets failed to concatenate 256-bit shifts back to 512-bits (split during 512-bit shuffle lowering as they don't have v32i16/v64i8 types).
2020-02-10 16:59:09 +00:00
David Stenberg 982944525c Revert "[InstCombine][DebugInfo] Fold constants wrapped in metadata"
This reverts commit b54a8ec1bc.

The commit triggered debug invariance (different output with/without
-g). The patch seems to have exposed a pre-existing invariance problem
in GlobalOpt, which I'll write a bug report for.
2020-02-10 17:58:33 +01:00
Kadir Cetinkaya 3606f792f4
[mlir] Delete unused header 2020-02-10 17:54:09 +01:00
Saleem Abdulrasool 14798b4465 unwind: rename `__personality_routine` to `_Unwind_Personality_Fn`
This patch renames `__personality_routine` to `_Unwind_Personality_Fn`
in `unwind.h`. Both `unwind.h` from clang and GCC headers use this name
instead of `__personality_routine`. With this patch one is also able to
build libc++abi with libunwind support on Windows.

Patch by Markus Böck!
2020-02-10 08:52:31 -08:00
Tobias Gysi 1555d7f729 [mlir] subview op lowering for target memrefs with const offset
The current standard to llvm conversion pass lowers subview ops only if
dynamic offsets are provided. This commit extends the lowering with a
code path that uses the constant offset of the target memref for the
subview op lowering (see Example 3 of the subview op definition for an
example) if no dynamic offsets are provided.

Differential Revision: https://reviews.llvm.org/D74280
2020-02-10 17:35:17 +01:00
Stanislav Mekhanoshin ed3527c648 [AMDGPU] Split R600 and GCN subregs
These are generated and do not need to have the same values.
We are defining separate subregs for R600 and GCN but then
using AMDGPU subregs on R600.

Differential Revision: https://reviews.llvm.org/D74248
2020-02-10 08:29:56 -08:00
James Henderson eea9040f42 [DebugInfo][test] Fix host endian test issue
The test previously assumed that the host was little endian, which broke
the big endian build bots.
2020-02-10 16:23:30 +00:00
Simon Pilgrim 06617c4522 [X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.

This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.

There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.

REAPPLIED rGe82e17d4d4ca after reversion at rG39eade73a567 - fixed offset matching in matchShuffleAsBitRotate.
2020-02-10 16:16:56 +00:00
LLVM GN Syncbot 4b1df7356a [gn build] Port 0151ddc2e8 2020-02-10 15:56:57 +00:00