b107a22afb
[X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests
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The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include
guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted
environment since it expects stdlib.h to be available - which is not the case
in these internal clang codegen tests).
This patch removes this hack and instead passes -ffreestanding to clang cc1.
Differential Revision: https://reviews.llvm.org/D24825
llvm-svn: 282581
2016-09-28 11:59:09 +00:00
f43e4a1728
[AVX-512] Remove masked integer mullo builtins and replace with native IR.
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llvm-svn: 280597
2016-09-03 19:19:49 +00:00
0e18976b8d
[AVX-512] Remove masked integer add/sub builtins and replace with native IR.
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llvm-svn: 280596
2016-09-03 18:29:35 +00:00
abb2b54ad3
After PR28761 use -Wall with -Werror in builtins tests to identify
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possible problems in headers.
llvm-svn: 277696
2016-08-04 06:02:50 +00:00
f5a8837e1b
[X86][AVX512] Converted the VBROADCAST intrinsics to generic IR
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llvm-svn: 274544
2016-07-05 12:59:33 +00:00
7dac6fbdf8
[Clang][BuiltIn][AVX512] adding _mm{|256|512}_mask_cvt{s|us|}epi16_storeu_epi8 intrinsics
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Differential Revision: http://reviews.llvm.org/D21729
llvm-svn: 274532
2016-07-05 08:08:01 +00:00
70d4bb566c
Update the expected masked load/store intrinsics names in tests
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The mangling of their names was changed in order to support arbitrary addrspace pointers as arguments in rL274043.
llvm-svn: 274044
2016-06-28 18:28:45 +00:00
79f53ca0b5
[AVX512] Replace masked unpack builtins with shufflevector and selects.
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llvm-svn: 273533
2016-06-23 06:36:42 +00:00
d1691c7026
[AVX512] Replace masked integer cmp and ucmp builtins with native IR.
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llvm-svn: 273378
2016-06-22 04:47:58 +00:00
a54c21e742
[AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.
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llvm-svn: 272787
2016-06-15 14:06:34 +00:00
68738332b8
[AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version.
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llvm-svn: 272452
2016-06-11 03:31:13 +00:00
d4273a425e
[AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics.
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llvm-svn: 272451
2016-06-11 03:31:07 +00:00
aadb876200
[AVX512] Emit select instruction instead of using x86 specific instrinsics.
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This will allow us to remove the x86 instrinics from the backend.
Differential Revision: http://reviews.llvm.org/D21060
llvm-svn: 272141
2016-06-08 13:59:20 +00:00
f51cc07719
[AVX512] Convert masked palignr builtins directly to native IR similar to the other palignr builtins, but with a select to handle masking.
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llvm-svn: 271873
2016-06-06 06:13:01 +00:00
4b060e31c9
[AVX512] Convert masked load builtins to generic masked load intrinsics instead of the x86 specific ones.
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This will allow the x86 intrinsics to be removed from the backend.
llvm-svn: 271253
2016-05-31 06:58:07 +00:00
6e891fbdd2
[AVX512] Emit generic masked store instrinsics instead of using x86 specific intrinsics.
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This will allow us to remove the x86 instrinics from the backend.
llvm-svn: 271246
2016-05-31 01:50:10 +00:00
e871785eb6
[Clang][avx512][Builtin] Adding intrinsics for cvtw2mask{128|256|512} instruction set
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Differential Revision: http://reviews.llvm.org/D19766
llvm-svn: 268385
2016-05-03 14:12:23 +00:00
de8d3753d3
[clang][AVX512][Builtin] Adding intrinsics for the SAD instruction set.
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Differential Revision: http://reviews.llvm.org/D19591
llvm-svn: 267942
2016-04-28 21:21:08 +00:00
533e065bdc
[Clang][BuiltIn][AVX512] Adding intrinsics fot align{d|q} and palignr instruction set
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Differential Revision: http://reviews.llvm.org/D19588
llvm-svn: 267876
2016-04-28 12:47:30 +00:00
8938e836c4
[Clang][AVX512][BuiltIn] Adding support to intrinsics of VPERMD and VPERMW instruction set
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Differential Revision: http://reviews.llvm.org/D19195
llvm-svn: 267380
2016-04-25 05:32:35 +00:00
c2b6128a8f
[Clang][AVX512][Builtin] Adding support for VBROADCAST and VPBROADCASTB/W/D/Q instruction set
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Differential Revision: http://reviews.llvm.org/D19012
llvm-svn: 266195
2016-04-13 12:58:01 +00:00
074edd7c1e
[Clang][AVX512][Builtin] Adding supporting to intrinsics of cvt{b|d|q}2mask{128|256|512} and cvtmask2{b|d|q}{128|256|512} instruction set.
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Differential Revision: http://reviews.llvm.org/D19009
llvm-svn: 266188
2016-04-13 10:49:37 +00:00
07525091e6
[Clang][AVX512][BuiltIn] Adding avx512 ( ptest{n}m{b|w}{128|256|512} ) builtin to clang
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Differential Revision: http://reviews.llvm.org/D18924
llvm-svn: 265928
2016-04-11 10:22:07 +00:00
fa7ccc5bcf
[Clang][AVX512][BuiltIn] Adding avx512 ( store ) builtin to clang
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Differential Revision: http://reviews.llvm.org/D18925
llvm-svn: 265895
2016-04-10 10:51:04 +00:00
def78750b7
[CLANG][avx512][BUILTIN] Adding fixupimm{pd|ps|sd|ss}
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getexp{sd|ss} getmant{sd|ss} kunpck{di|si} loada{pd|ps} loaddqu{di|hi|qi|si} max{sd|ss} min{sd|ss} kmov16 builtins to clang
Differential Revision: http://reviews.llvm.org/D18215
llvm-svn: 264574
2016-03-28 12:23:09 +00:00
912be16a0e
[CLANG][AVX512][BUILTIN] Adding vpmultishiftqb{128|256|512}
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Differential Revision: http://reviews.llvm.org/D17914
llvm-svn: 262817
2016-03-07 08:29:10 +00:00
1ad03e7f01
[CLANG][AVX512][BUILTIN] movdqu{qi|hi} {128|256|512}
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Differential Revision: http://reviews.llvm.org/D17814
llvm-svn: 262609
2016-03-03 11:34:52 +00:00
abbe34bce6
[Clang][AVX512][BUILTIN] Adding PSRL{W|WI}{128|256|512}
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Differential Revision: http://reviews.llvm.org/D17754
llvm-svn: 262593
2016-03-03 08:55:20 +00:00
3df95e711f
[CLANG] [AVX512] [BUILTIN] Adding PSRA{W|WI}{128|256|512}.
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Differential Revision: http://reviews.llvm.org/D17706
llvm-svn: 262481
2016-03-02 12:06:06 +00:00
d15c95a793
[CLANG] [AVX512] [BUILTIN] Adding PSRAV
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Differential Revision: http://reviews.llvm.org/D17699
llvm-svn: 262471
2016-03-02 09:05:46 +00:00
0165e7669c
[CLANG][AVX512][BUILTIN] Adding PSRLV builtin
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Differential Revision: http://reviews.llvm.org/D17718
llvm-svn: 262326
2016-03-01 13:03:45 +00:00
431b0e18b4
[CLANG] [AVX512] [BUILTIN] Adding PSLL{V|W|Wi}{128|256|512} builtin
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Differential Revision: http://reviews.llvm.org/D17685
llvm-svn: 262177
2016-02-28 07:39:34 +00:00
6c317515e4
[CLANG] [AVX512] [BUILTIN] Adding PSHUF{L|H}W{128|256|512} builtin to clang .
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Differential Revision: http://reviews.llvm.org/D17539
llvm-svn: 261755
2016-02-24 17:39:35 +00:00
7a33dce4ef
[CLANG] [AVX512] [BUILTIN] Adding pmovzx{b|d|w}{w|d|q}{128|256|512} builtin to clang
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Differential Revision: http://reviews.llvm.org/D16961
llvm-svn: 261471
2016-02-21 14:00:11 +00:00
7cdb72f7ea
[CLANG] [AVX512] [BUILTIN] Adding pmovsx{b|d|w}{w|d|q}{128|256|512} builtin to clang
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Differential Revision: http://reviews.llvm.org/D16955
llvm-svn: 261196
2016-02-18 09:09:34 +00:00
cd875efa78
Canonicalize some of the x86 builtin tests and either remove or comment
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about optimization options.
llvm-svn: 250271
2015-10-14 05:40:21 +00:00
cbe6411401
Fix the SSE4 byte sign extension in a cleaner way, and more thoroughly
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test that our intrinsics behave the same under -fsigned-char and
-funsigned-char.
This further testing uncovered that AVX-2 has a broken cmpgt for 8-bit
elements, and has for a long time. This is fixed in the same way as
SSE4 handles the case.
The other ISA extensions currently work correctly because they use
specific instruction intrinsics. As soon as they are rewritten in terms
of generic IR, they will need to add these special casts. I've added the
necessary testing to catch this however, so we shouldn't have to chase
it down again.
I considered changing the core typedef to be signed, but that seems like
a bad idea. Notably, it would be an ABI break if anyone is reaching into
the innards of the intrinsic headers and passing __v16qi on an API
boundary. I can't be completely confident that this wouldn't happen due
to a macro expanding in a lambda, etc., so it seems much better to leave
it alone. It also matches GCC's behavior exactly.
A fun side note is that for both GCC and Clang, -funsigned-char really
does change the semantics of __v16qi. To observe this, consider:
% cat x.cc
#include <smmintrin.h>
#include <iostream>
int main() {
__v16qi a = { 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
__v16qi b = _mm_set1_epi8(-1);
std::cout << (int)(a / b)[0] << ", " << (int)(a / b)[1] << '\n';
}
% clang++ -o x x.cc && ./x
-1, 1
% clang++ -funsigned-char -o x x.cc && ./x
0, 1
However, while this may be surprising, both Clang and GCC agree.
Differential Revision: http://reviews.llvm.org/D13324
llvm-svn: 249097
2015-10-01 23:40:12 +00:00
1998eb2077
[X86][AVX512BW] add convert i16 to i8 and unpack intrinsics
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Differential Revision: http://reviews.llvm.org/D11564
llvm-svn: 243514
2015-07-29 12:34:20 +00:00
7d99966e91
[X86][AVX512BW] add madd and maddubs intrinsics
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Differential Revision: http://reviews.llvm.org/D11420
llvm-svn: 242986
2015-07-23 07:07:25 +00:00
d4419ca657
[X86][AVX512BW] add clang intrinsics for pmulhrsw / pmulhuw / pmulhw
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also made minor fix in "test_mm512_maskz_permutex2var_epi16"
Differential Revision: http://reviews.llvm.org/D11336
llvm-svn: 242635
2015-07-19 08:47:31 +00:00
4002ce4834
[X86][AVX512BW] Add more intrinsics support:
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Blend, abs, packs, adds, subs, avg, max, min, permute.
all the intrinsics are covered by tests
review:
http://reviews.llvm.org/D10799
llvm-svn: 240937
2015-06-29 12:16:40 +00:00
23fccde1b1
AVX-512: Changed CC parameter in "cmp" intrinsic
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from i8 to i32 according to the Intel Spec
llvm-svn: 236980
2015-05-11 09:03:41 +00:00
35dc8c0944
AVX-512: added intrinsics for KNL and SKX
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by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 235986
2015-04-28 13:28:01 +00:00
b4789096c0
[X86] Add AVX512 integer comparison intrinsics for word and byte vectors.
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llvm-svn: 227079
2015-01-26 09:24:10 +00:00
b9f3a911c9
[AVX512] Added VPCMPEQ intrinisics to headers.
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Added tests.
Patch by Maxim Blumenthal <maxim.blumenthal@intel.com>
llvm-svn: 219319
2014-10-08 17:18:13 +00:00
Elad Cohen