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19 Commits

Author SHA1 Message Date
Craig Topper 965de2c197 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper 3657fe4b17 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Bill Wendling 063f55ffdd Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Craig Topper 8cc9388073 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Craig Topper 271064e873 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Craig Topper 786bdb9e14 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Craig Topper 0d0be47d03 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
llvm-svn: 140997
 2011-10-03 08:14:29 +00:00
Craig Topper 285bc34089 Test updates that were supposed to go with r140993. 
llvm-svn: 140994
 2011-10-03 07:53:59 +00:00
Craig Topper 7aea69d949 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
llvm-svn: 140974
 2011-10-02 21:08:12 +00:00
Craig Topper d07a59f288 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper 88cb33e0d4 Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Craig Topper 45faba98b4 Fix VEX decoding in i386 mode. Fixes PR11008. 
llvm-svn: 140515
 2011-09-26 05:12:43 +00:00
Kevin Enderby 54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Kevin Enderby 7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
Eli Friedman 0318036c4d Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
llvm-svn: 135337
 2011-07-16 02:41:28 +00:00