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Author SHA1 Message Date
Alex Bradbury 65d6ea5e68 [RISCV] Codegen support for RV32F floating point comparison operations 
This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.

llvm-svn: 328104
 2018-03-21 15:11:02 +00:00