We need "xgot" flag in the MipsAsmParser to implement correct expansion
of some pseudo instructions in case of using 32-bit GOT (XGOT).
MipsAsmParser does not have reference to MipsSubtarget but has a
reference to "feature bit set".
llvm-svn: 372220
These two options enable/disable emission of R_{MICRO}MIPS_JALR fixups along
with PIC calls. The linker may then try to turn PIC calls into direct jumps.
By default, these fixups do get emitted by the backend, use
'-mno-relax-pic-calls' to omit them.
Differential revision: https://reviews.llvm.org/D56878
llvm-svn: 351579
In order to disable PIC and to match GCC behaviour, -mno-abicalls
option is neccessary. When -fno-[pic/PIC] is used witout -mno-abicalls,
warning is reported. An error is reported when -fno-pic or -fno-PIC is
used in combination with -mabicalls.
In this commit, test case is added.
Depends on D44381.
Differential Revision: https://reviews.llvm.org/D44684
llvm-svn: 331640
In order to disable PIC and to match GCC behaviour, -mno-abicalls
option is neccessary. When -fno-[pic/PIC] is used witout -mno-abicalls,
warning is reported. An error is reported when -fno-pic or -fno-PIC is
used in combination with -mabicalls.
Depends on D44381.
Differential Revision: https://reviews.llvm.org/D44684
llvm-svn: 331636
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.
This option is accepted when targeting MIPS revision two or later.
The migitation strategy suggested by MIPS for these processors is to
use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.
These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.
These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.
These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.
Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS
ISA in future, e.g. retpoline style solutions.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D43487
llvm-svn: 325651
-mbranch-likely and -mno-branch-likely are used in some build systems for
some MIPS targets. Accept these options but ignore them as they are an
(de)optimiztion hint, and that branch likely instructions were deprecated
but not removed from MIPS32 and MIPS64 ISAs.
Reviewers: atanasyan, nitesh.jain
Differential Revision: https://reviews.llvm.org/D38168
llvm-svn: 314213
In patch r205628 using abs.[ds] instruction is forced, as they should behave
in accordance with flags Has2008 and ABS2008. Unfortunately for revisions
prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when
working with NaNs. To generate a sequence which always produce a correct
result but also to allow user more control on how his code is compiled,
option -mabs is added where user can choose legacy or 2008.
By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6
use abs2008 mode by default.
Patch by Aleksandar Beserminji
Differential Revision: https://reviews.llvm.org/D35982
llvm-svn: 311669
As clang defaults to -mno-abicalls when using -fno-pic for N64, implicitly use
-mgpopt in that case.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D36315
llvm-svn: 310714
While we do not support `-mshared / -mno-shared` properly, show warning
and ignore `-mlong-calls` option in case of implicitly or explicitly
provided `-mabicalls` option.
Differential revision: https://reviews.llvm.org/D36551
llvm-svn: 310614
The -mabicalls option does not make sense in the case of non position
independent code for the N64 ABI. After this change the driver shows a
warning that -mabicalls is ignored in that case.
Differential revision: https://reviews.llvm.org/D36550
llvm-svn: 310613
Add support for the -membedded-data option which places constant data in
the .rodata section, rather than the .sdata section.
Reviewers: atanasyan, nitesh.jain
Differential Revision: https://reviews.llvm.org/D35914
llvm-svn: 309935
Add support for -m(no-)extern-data when using -mgpopt in the driver. It is
enabled by default in the backend.
Reviewers: atanasyan, slthakur
Differential Revision: https://reviews.llvm.org/D35550
llvm-svn: 308879
This patch teaches the driver to pass -mgpopt by default to the backend when it
is supported, i.e. we are using -mno-abicalls.
Reviewers: atanasyan, slthakur
Differential Revision: https://reviews.llvm.org/D35548
This version fixes a logic error that generated warnings incorrectly and
gets rid of spurious arguments to the backend when -mgpopt is not used.
llvm-svn: 308619
This patch teaches the driver to pass -mgpopt by default to the backend when it
is supported, i.e. we are using -mno-abicalls.
Reviewers: atanasyan, slthakur
Differential Revision: https://reviews.llvm.org/D35548
This version fixes a logic error that generated warnings incorrectly.
llvm-svn: 308458
This patch teaches the driver to pass -mgpopt by default to the backend when it
is supported, i.e. we are using -mno-abicalls.
Reviewers: atanasyan, slthakur
Differential Revision: https://reviews.llvm.org/D35548
llvm-svn: 308431
Check the `-mlong-calls` command line option and pass the `long-calls`
feature flag to the backend. Handling of this feature flag in the backend
needs to be implemented by a separate commit.
llvm-svn: 307386
This patch adds the commandline option -mcompact-branches={never,optimal,always),
which controls how LLVM generates compact branches for MIPSR6 targets. By default,
the compact branch policy is 'optimal' where LLVM will generate the most
appropriate branch for any situation. The 'never' and 'always' policy will disable
or always generate compact branches wherever possible respectfully.
Reviewers: dsanders, vkalintiris, atanasyan
Differential Revision: http://reviews.llvm.org/D20729
llvm-svn: 271000
Summary:
If the driver is only given -msoft-float/-mfloat-abi=soft or -msingle-float,
we should refrain from propagating -mfpxx, unless it was explicitly given on the
command line.
Reviewers: atanasyan, dsanders
Reviewed By: atanasyan, dsanders
Subscribers: cfe-commits, mpf
Differential Revision: http://reviews.llvm.org/D10387
llvm-svn: 239818
This patch generates a warning for invalid combination of '-mnan' and
'-march' options, it properly sets NaN encoding for a given '-march',
and it passes a proper NaN encoding to the assembler.
Patch by Vladimir Radosavljevic.
Differential Revision: http://reviews.llvm.org/D8170
llvm-svn: 234882
Also added the testcase that should have been in r215194.
This behaviour has surprised me a few times now. The problem is that the
generated MipsSubtarget::ParseSubtargetFeatures() contains code like this:
if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true;
so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to
true'. In this case, (and the similar -modd-spreg case) I'd like the code to be
IsABICalls = (Bits & Mips::FeatureABICalls) != 0;
or possibly:
if ((Bits & Mips::FeatureABICalls) != 0)
IsABICalls = true;
else
IsABICalls = false;
and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default
(on some triples).
llvm-svn: 215211
Summary: The initial support for NaN2008 was added to the back-end in r206396.
Reviewers: atanasyan
Reviewed By: atanasyan
Differential Revision: http://reviews.llvm.org/D3448
llvm-svn: 208220
These options specify 64-bit FP registers and 32-bit FP registers respectively.
When using -mfp32, the FPU has 16x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
two single-precision registers).
When using -mfp64, the FPU has 32x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
with one single-precision register and has an additional 32-bits).
MSA requires -mfp64.
llvm-svn: 192899
This patch adds -mmsa and -mno-msa to the options supported by
clang to enable and disable support for MSA.
When MSA is enabled, a predefined macro '__mips_msa' is defined to 1.
Patch by Daniel Sanders
llvm-svn: 188184
Lots of tests are using an explicit target triple w/o first checking that the
target is actually available. Add a REQUIRES clause to a bunch of them. This should
hopefully unbreak bots which don't configure w/ all targets enabled.
llvm-svn: 159949
Simon Atanasyan