37b0736bdc
Pseudos default to 4byte size, let the instruction size field notice
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that branch tables are special.
llvm-svn: 119954
2010-11-21 23:38:19 +00:00
c01d679928
Add encoding for ARM "trap" instruction.
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llvm-svn: 119938
2010-11-21 11:05:29 +00:00
e040a46eb3
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
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llvm-svn: 119918
2010-11-21 01:26:01 +00:00
2aff392af9
Fix ARM LDR* post-indexed operand encoding.
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llvm-svn: 119869
2010-11-19 23:14:43 +00:00
48bf4f8e56
Fix encoding for ARM MLS instruction.
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llvm-svn: 119855
2010-11-19 22:22:37 +00:00
09d7bfd886
Add ARM encoding information for STRD.
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llvm-svn: 119852
2010-11-19 22:14:31 +00:00
5a77b8b5c4
Shuffle things around a bit to keep like things together. Tidy up formatting.
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llvm-svn: 119851
2010-11-19 22:06:57 +00:00
6e9aace4f3
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
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llvm-svn: 119846
2010-11-19 21:35:06 +00:00
d6e5c9f2fe
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
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llvm-svn: 119841
2010-11-19 21:14:02 +00:00
4a22eba616
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
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llvm-svn: 119840
2010-11-19 21:07:51 +00:00
003c6e700b
Add ARM binary encoding information for the rest of the indexed loads.
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llvm-svn: 119821
2010-11-19 19:41:26 +00:00
76aed40813
ARM LDRD binary encoding.
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llvm-svn: 119812
2010-11-19 18:16:46 +00:00
2aeb8b9361
Minor cleanups to a few llvm_unreachable() calls.
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llvm-svn: 119767
2010-11-19 00:27:09 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
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Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
a391c97bd0
ARM Encoding information for UXTAH and friends.
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llvm-svn: 119753
2010-11-18 23:24:22 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
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the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
cfb66204b7
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
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just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
8e7f8df4a2
Refactor a few ARM load instructions to better parameterize things and re-use
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common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
56f471726c
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
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it as such. Add some encoding information.
llvm-svn: 119588
2010-11-17 23:33:14 +00:00
08c562bba6
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
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in the MC lowering process.
llvm-svn: 119559
2010-11-17 21:05:55 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
...
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
8839775df6
More ARM encoding bits. LDRH now encodes properly.
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llvm-svn: 119529
2010-11-17 18:11:11 +00:00
9898ac97fd
Proper encoding for VLDM and VSTM instructions. The register lists for these
...
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
llvm-svn: 119460
2010-11-17 04:32:08 +00:00
a8974af320
Use the correct variable names so that the encodings will be correct.
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llvm-svn: 119403
2010-11-16 23:44:49 +00:00
e600aba989
ARM conditional mov encoding fix.
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llvm-svn: 119354
2010-11-16 18:13:42 +00:00
3bd60eff26
- Remove dead patterns.
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- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
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llvm-svn: 119180
2010-11-15 20:47:07 +00:00
40a7f57d0d
Nuke redundant encoding bit set.
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llvm-svn: 119164
2010-11-15 18:17:24 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
9430eb489c
Comment out the defms until they're activated.
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llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
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llvm-svn: 118998
2010-11-13 10:43:34 +00:00
f2fa04acfc
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
79ff5238e9
Conditional moves are slightly more expensive than moves.
...
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
2bcb8daa44
Add conditional move of large immediate.
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llvm-svn: 118968
2010-11-13 02:25:14 +00:00
1aa5863a3e
Swap multiclass operand order for consistency with other patterns.
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llvm-svn: 118965
2010-11-13 01:28:30 +00:00
69fd90e661
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
2f790749e8
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
9c40af415f
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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llvm-svn: 118945
2010-11-12 23:46:13 +00:00
f478cf9685
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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llvm-svn: 118938
2010-11-12 23:03:38 +00:00
0fc8084a64
Add conditional mvn instructions.
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llvm-svn: 118935
2010-11-12 22:42:47 +00:00
e09122b46b
Zap a copy/paste-o bit of dead code.
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llvm-svn: 118926
2010-11-12 21:29:10 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
3fd741191d
Fill in the default predication bits for ARM unconditional branch.
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llvm-svn: 118907
2010-11-12 18:13:26 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
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llvm-svn: 118829
2010-11-11 20:05:40 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
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llvm-svn: 118794
2010-11-11 16:55:29 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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llvm-svn: 118767
2010-11-11 01:55:59 +00:00
Eric Christopher