46662e0f91
Coding style fixes. Added comments.
...
llvm-svn: 132063
2011-05-25 17:32:06 +00:00
85ec52125b
Remove unused OpcodeMask enumerator.
...
llvm-svn: 132062
2011-05-25 17:02:53 +00:00
58b09c9366
Fix MSVC warning: "is out of range for enum constant"
...
MSVC doesn't support 64 bit enum.
OpcodeMask is not used anywhere in the code base.
llvm-svn: 132057
2011-05-25 15:58:10 +00:00
a51604e511
Restore an accidentally removed comment.
...
llvm-svn: 132044
2011-05-25 04:48:17 +00:00
6b66ee1865
Move some code to a more logical place.
...
llvm-svn: 132043
2011-05-25 04:45:29 +00:00
3088e0a179
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
...
fixes <rdar://problem/9495913>
llvm-svn: 132042
2011-05-25 04:45:27 +00:00
310b3472ec
Change the order of tBX's operands so that the predicate operands come after the
...
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007 >
llvm-svn: 132041
2011-05-25 04:45:23 +00:00
012247e60c
Rename tBX_Rm to tBX.
...
llvm-svn: 132040
2011-05-25 04:45:20 +00:00
deaf994ff0
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
...
reflect their actual meaning and match the ARM instructions.
llvm-svn: 132039
2011-05-25 04:45:14 +00:00
fc9bae6f8b
Replace the -unwind-tables option with a per function flag. This is more
...
LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.
llvm-svn: 132033
2011-05-25 03:44:17 +00:00
aac670c1c8
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 132030
2011-05-25 02:20:00 +00:00
5445213a25
Fix PR9762
...
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
llvm-svn: 132026
2011-05-25 00:35:03 +00:00
1b724948e9
Implement the arm 'L' asm modifier.
...
Part of rdar://9119939
llvm-svn: 132024
2011-05-24 23:27:13 +00:00
b1dda56ac2
Implement the immediate part of the 'B' modifier.
...
Part of rdar://9119939
llvm-svn: 132023
2011-05-24 23:15:43 +00:00
d4562566b4
Add more unimplemented asm modifiers and some documentation of what they
...
do.
Part of rdar://9119939.
llvm-svn: 132015
2011-05-24 22:27:43 +00:00
7617883ce3
Add support for the arm 'y' asm modifier.
...
Fixes part of rdar://9444657
llvm-svn: 132011
2011-05-24 22:10:34 +00:00
2db176c4c1
Enable printing of immediates that do not fit in 16-bit. .cprestore can have
...
offsets that are larger than 0x10000.
llvm-svn: 132003
2011-05-24 21:22:21 +00:00
5e16c6a9b2
Implement byval structure argument passing. The following limitations or
...
deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
llvm-svn: 131986
2011-05-24 19:18:33 +00:00
5de2375db8
Remove dead code.
...
llvm-svn: 131974
2011-05-24 18:27:52 +00:00
97019c709d
Add a method to TargetRegisterInfo to get the register number that the Win64 EH
...
scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).
llvm-svn: 131969
2011-05-24 16:57:53 +00:00
88f9137fd7
- Teach SelectionDAG::isKnownNeverZero to return true (op x, c) when c is
...
non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.
rdar://9490949
llvm-svn: 131948
2011-05-24 01:48:22 +00:00
cb4a1a8d3f
Simplify offset calculation of stack frame objects for $gp restore location and
...
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
llvm-svn: 131942
2011-05-24 00:23:52 +00:00
dfb8cda11f
Expand f64 FPOW.
...
llvm-svn: 131928
2011-05-23 22:23:58 +00:00
6af5bd2537
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
...
llvm-svn: 131927
2011-05-23 22:16:43 +00:00
9dbb45b596
Fixes related to coding style.
...
llvm-svn: 131922
2011-05-23 21:13:59 +00:00
90d96f44ce
Fix MipsAsmPrinter::printSavedRegsBitmaskChange. Remove functions and variables
...
in MipsFunctionInfo that are no longer used.
llvm-svn: 131917
2011-05-23 20:34:30 +00:00
d71ed9431a
clarify this, apparently it is confusing :)
...
llvm-svn: 131916
2011-05-23 20:17:44 +00:00
f9e5750fc8
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
llvm-svn: 131915
2011-05-23 20:16:59 +00:00
bc90690b24
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
...
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
llvm-svn: 131894
2011-05-23 01:57:17 +00:00
e240dc52ff
add a missing alias to make us more bug compatible with gcc, PR9378
...
llvm-svn: 131874
2011-05-22 22:31:57 +00:00
4cd5187f5b
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
...
llvm-svn: 131868
2011-05-22 21:41:23 +00:00
bfe2c24c80
add a note.
...
llvm-svn: 131863
2011-05-22 18:28:46 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
bbc40ac474
move PR9408 here.
...
llvm-svn: 131841
2011-05-22 05:45:06 +00:00
4c0d9e2249
add a copy ctor to TargetLibraryInfo.
...
llvm-svn: 131806
2011-05-21 20:09:13 +00:00
e30b70073a
X86: smulo -> add is now done target-independently in DAGCombiner, remove the patterns.
...
llvm-svn: 131801
2011-05-21 18:32:01 +00:00
faeb520c97
Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It
...
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
llvm-svn: 131787
2011-05-21 04:13:49 +00:00
2df6c010aa
Use the correct register to access stack frame objects.
...
llvm-svn: 131785
2011-05-21 03:01:03 +00:00
f084fcd7fe
Insert instructions that copy $sp to or from $fp at the right locations.
...
llvm-svn: 131784
2011-05-21 02:29:26 +00:00
0837692ac6
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
...
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
llvm-svn: 131767
2011-05-20 23:22:14 +00:00
60afcc2a6f
Add fast-isel support for byval calls on x86.
...
llvm-svn: 131764
2011-05-20 22:21:04 +00:00
7c619f174a
In CC_MipsO32, allocate a stack space regardless of whether the argument is
...
passed in register or on the stack.
llvm-svn: 131758
2011-05-20 21:39:54 +00:00
cae19e8671
Define functions that get/set maximum call frame size.
...
llvm-svn: 131752
2011-05-20 20:11:17 +00:00
652bfdb1ab
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
1866808384
fixes target address tBL and tBLX and sets relocation type
...
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
2011-05-20 20:01:01 +00:00
91f1d24736
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
...
rdar://problem/8614450
llvm-svn: 131746
2011-05-20 19:04:40 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
4fcd8250ae
Revert accidental commit.
...
llvm-svn: 131739
2011-05-20 17:38:48 +00:00
0bf26746d9
Rename the "sandybridge" subtarget to "corei7-avx", for GCC compatibility.
...
llvm-svn: 131730
2011-05-20 15:11:26 +00:00
cc7a928885
Remove noisy semicolons.
...
llvm-svn: 131724
2011-05-20 09:20:25 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
llvm-svn: 131714
2011-05-20 02:30:51 +00:00
7489faa0c1
Remove code that creates unnecessary frame objects.
...
llvm-svn: 131711
2011-05-20 01:45:06 +00:00
d738c0f7c9
Define variables and functions in MipsFunctionInfo.
...
This is the first of a series of patches that attempt to simplify handling of
stack frame objects.
llvm-svn: 131710
2011-05-20 01:17:58 +00:00
552f8c4819
Don't attempt to tail call optimize for Win64.
...
llvm-svn: 131709
2011-05-20 00:59:28 +00:00
e8d2e9eb35
Revert r131664 and fix it in instcombine instead. rdar://9467055
...
llvm-svn: 131708
2011-05-20 00:54:37 +00:00
22da799428
Add fast-isel support for zeroext and signext ret instructions on x86.
...
llvm-svn: 131689
2011-05-19 22:16:13 +00:00
4014e5e208
Oddly people want to use the 'r' constraint for fp constants on x86.
...
Fixes rdar://9218925
Fixes PR9601
llvm-svn: 131682
2011-05-19 21:33:47 +00:00
d0c937d4b2
This fixes one divergence between LLVM and binutils for ARM in the
...
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
2011-05-19 20:55:25 +00:00
0fc5e89c82
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
...
Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
2011-05-19 20:32:34 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
...
llvm-svn: 131668
2011-05-19 20:29:48 +00:00
2b9bd38678
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
...
llvm-svn: 131664
2011-05-19 18:57:12 +00:00
05fd5aa1d0
Increase number of available registers when target is MIPS32.
...
llvm-svn: 131660
2011-05-19 18:25:03 +00:00
92ab6db6c8
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
...
llvm-svn: 131657
2011-05-19 18:06:05 +00:00
c72240bbd9
Reverting 131641 to investigate 'bot complaint.
...
llvm-svn: 131654
2011-05-19 17:54:42 +00:00
eca54e4e6d
80 columns.
...
llvm-svn: 131649
2011-05-19 17:34:53 +00:00
d1465bd68b
Fix data layout string. i64 is aligned to 64 bit boundaries.
...
llvm-svn: 131642
2011-05-19 17:21:09 +00:00
b476b0cc9f
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
...
pseudos. rdar://problem/8614450
llvm-svn: 131641
2011-05-19 16:59:50 +00:00
9eb5a410bd
Use the correct register class for Cell varargs spilling. This fixes all of the
...
verifier failures in the CodeGen/CellSPU tests.
llvm-svn: 131631
2011-05-19 04:44:19 +00:00
6d9e1c7c2e
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
...
llvm-svn: 131630
2011-05-19 04:15:07 +00:00
41025dc95b
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
...
llvm-svn: 131627
2011-05-19 03:11:06 +00:00
dadd73390f
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
...
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
llvm-svn: 131626
2011-05-19 02:56:28 +00:00
58eafde58b
Reuse the TargetInstrDesc.
...
llvm-svn: 131625
2011-05-19 02:56:23 +00:00
00b780e280
Correctly constrain a register class when computing frame offsets, as the Thumb2
...
add instruction takes an rGPR. This fixes the last of PR8825.
llvm-svn: 131619
2011-05-19 02:18:27 +00:00
6fc94dd687
Revert unintentional commit.
...
llvm-svn: 131597
2011-05-18 23:13:10 +00:00
1754a25977
More instcombine simplifications towards better debug locations.
...
llvm-svn: 131596
2011-05-18 23:11:30 +00:00
b9bef106c6
Add missing mayLoad / mayStore flags to instruction definitions without patterns,
...
which fixes all of the CodeGen/MBlaze verifier failures.
llvm-svn: 131595
2011-05-18 23:03:10 +00:00
9ddeceff19
Reserve the segment registers on x86 to fix verifier failures in any code that
...
uses them.
llvm-svn: 131591
2011-05-18 22:24:48 +00:00
8b2e426555
Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.
...
llvm-svn: 131587
2011-05-18 21:54:32 +00:00
1d11720ae4
Handle perfect shuffle case that generates a vrev for vectors of floats.
...
Add test case.
llvm-svn: 131582
2011-05-18 21:44:54 +00:00
ec645bf75d
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
...
llvm-svn: 131578
2011-05-18 21:25:14 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
llvm-svn: 131565
2011-05-18 20:32:41 +00:00
f4e832b14e
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
...
llvm-svn: 131560
2011-05-18 19:59:50 +00:00
522fbfea3b
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
...
llvm-svn: 131555
2011-05-18 18:59:17 +00:00
80632c91b0
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
...
llvm-svn: 131553
2011-05-18 18:47:27 +00:00
bbdcd17d44
PTX: add flag to disable mad/fma selection
...
Patch by Dan Bailey
llvm-svn: 131537
2011-05-18 15:42:23 +00:00
48b182c3a4
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
...
Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
2011-05-18 06:42:21 +00:00
f9839e4257
Fix typo.
...
llvm-svn: 131519
2011-05-18 02:29:50 +00:00
d7c55fe2ef
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
...
compare-and-swap intrinsics.
llvm-svn: 131518
2011-05-18 02:20:07 +00:00
33a67ddbd2
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
...
take r13, so we can just make it a GPR. This fixes PR8825.
llvm-svn: 131507
2011-05-17 23:26:20 +00:00
c5d272766f
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
...
were marked as taking a tGPR when in reality they take an rGPR.
llvm-svn: 131506
2011-05-17 23:11:12 +00:00
c7e291b354
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
...
llvm-svn: 131488
2011-05-17 20:48:40 +00:00
6f6b44d19d
Enable autodetect of popcnt
...
llvm-svn: 131476
2011-05-17 18:33:37 +00:00
7b27942fe7
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
...
This is r131438 with a couple small fixes.
llvm-svn: 131474
2011-05-17 18:29:03 +00:00
d000a2c26e
Clean up the mess created by r131467+r131469.
...
llvm-svn: 131471
2011-05-17 18:02:22 +00:00
c65d8eda7b
Revert 131467 due to buildbot complaint.
...
llvm-svn: 131469
2011-05-17 16:59:46 +00:00
3cf5308890
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
...
passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
llvm-svn: 131467
2011-05-17 16:45:55 +00:00
d8edb1d5cc
Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
...
with two different types, in cases where the index and the ptr had different
types.
llvm-svn: 131461
2011-05-17 08:31:57 +00:00
56a42ebf15
Update comment.
...
llvm-svn: 131459
2011-05-17 08:16:14 +00:00
a1d9e29552
Support XOR and AND optimization with no return value.
...
Finishes off rdar://8470697
llvm-svn: 131458
2011-05-17 08:10:18 +00:00
abfe3131e3
Couple less magic numbers.
...
llvm-svn: 131457
2011-05-17 07:50:41 +00:00
Akira Hatanaka