Commit Graph

72 Commits

Author SHA1 Message Date
Evan Cheng 175bd14967 Make sure Thumb2 uses the right call instructions.
llvm-svn: 77507
2009-07-29 21:26:42 +00:00
Evan Cheng 0d98d8b8b3 - Fix an obvious copy and paste error.
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
2009-07-29 20:10:36 +00:00
Evan Cheng c6d70ae063 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
llvm-svn: 77422
2009-07-29 02:18:14 +00:00
Evan Cheng c8bed03349 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
llvm-svn: 77364
2009-07-28 20:53:24 +00:00
David Goodwin 68bb69d6e3 Remove support for ORN to workaround <rdar://problem/7096522>.
llvm-svn: 77363
2009-07-28 20:51:25 +00:00
David Goodwin 865c6298d7 Add workaround for <rdar://problem/7098328>.
llvm-svn: 77340
2009-07-28 18:15:38 +00:00
David Goodwin e82862e24e Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
llvm-svn: 77329
2009-07-28 17:06:49 +00:00
Evan Cheng 780748d565 - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
2009-07-28 05:48:47 +00:00
David Goodwin 57b51d9f82 ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
llvm-svn: 77275
2009-07-27 23:34:12 +00:00
David Goodwin 007031d1b4 Thumb-2 does not have RSC.
llvm-svn: 77201
2009-07-27 16:39:05 +00:00
David Goodwin 782f242fd7 Add ".w" suffix for wide thumb-2 instructions.
llvm-svn: 77199
2009-07-27 16:31:55 +00:00
Evan Cheng f3a1fce8ae Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl ]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl 
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
2009-07-25 00:33:29 +00:00
Evan Cheng c64ce30c67 Uh. It would be useful to actually print the operand.
llvm-svn: 77004
2009-07-24 20:47:38 +00:00
Evan Cheng 666c912ce3 Make sure thumb2 jumptable entries are aligned.
llvm-svn: 76986
2009-07-24 18:20:44 +00:00
David Goodwin cdd405d804 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Evan Cheng dc99f07113 Thumb2 does not allow the use of "pc" register as part of the load / store address.
llvm-svn: 76909
2009-07-23 23:09:51 +00:00
Evan Cheng 95a73e2eab Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889
2009-07-23 18:26:03 +00:00
David Goodwin 6deba28c6f Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
llvm-svn: 76883
2009-07-23 17:06:46 +00:00
Evan Cheng e270d4a4dd Use getTargetConstant instead of getConstant since it's meant as an constant operand.
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
Evan Cheng 4b02b2f79c Don't forget D16 - D31 are clobbered by calls and sjlj eh.
llvm-svn: 76729
2009-07-22 06:46:53 +00:00
David Goodwin 711b9e809c CMP and TST define CPSR, not use it.
llvm-svn: 76489
2009-07-20 22:13:31 +00:00
Evan Cheng cd4cdd1157 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng 0f9cce7951 Add a thumb2 pass to insert IT blocks.
llvm-svn: 75218
2009-07-10 01:54:42 +00:00
Evan Cheng 1622d7b429 Fix ldm / stm unified syntax; add t2LDM_RET.
llvm-svn: 75188
2009-07-09 22:58:39 +00:00
Evan Cheng 7591d02c84 Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
Note, we are not yet generating these instructions.

llvm-svn: 75181
2009-07-09 22:21:59 +00:00
Evan Cheng ad93707e16 Correct comment.
llvm-svn: 75172
2009-07-09 20:40:44 +00:00
David Goodwin 22c2fba978 Use common code for both ARM and Thumb-2 instruction and register info.
llvm-svn: 75067
2009-07-08 23:10:31 +00:00
Evan Cheng e3a53c448b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
llvm-svn: 75048
2009-07-08 21:03:57 +00:00
David Goodwin 03ab0bbb24 Generalize opcode selection in ARMBaseRegisterInfo.
llvm-svn: 75036
2009-07-08 20:28:28 +00:00
David Goodwin af7451b674 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
llvm-svn: 75010
2009-07-08 16:09:28 +00:00
Evan Cheng d0611f9a37 Add Thumb2 movcc instructions.
llvm-svn: 74946
2009-07-07 20:39:03 +00:00
Evan Cheng d0f6324cdc Add Thumb2 pkhbt / pkhtb.
llvm-svn: 74895
2009-07-07 05:35:52 +00:00
Evan Cheng b24e51e2d9 Add some more Thumb2 multiplication instructions.
llvm-svn: 74889
2009-07-07 01:17:28 +00:00
Evan Cheng 40398233b7 Add bfc to armv6t2.
llvm-svn: 74868
2009-07-06 22:23:46 +00:00
Evan Cheng 0e8bde5910 Add thumb2 sign / zero extend with rotate instructions.
llvm-svn: 74755
2009-07-03 01:43:10 +00:00
Evan Cheng 6d9041100b Add Thumb2 load / store multiple instructions. Not used yet.
llvm-svn: 74749
2009-07-03 00:18:36 +00:00
Evan Cheng f30ee8820a t2LDR_PRE etc are loads.
llvm-svn: 74741
2009-07-03 00:08:19 +00:00
Evan Cheng 53cdf022b6 Added indexed stores.
llvm-svn: 74740
2009-07-03 00:06:39 +00:00
Evan Cheng 8ecd7eb3f7 Sign extending pre/post indexed loads.
llvm-svn: 74736
2009-07-02 23:16:11 +00:00
Evan Cheng 84c6cda2ef Thumb2 pre/post indexed loads.
llvm-svn: 74696
2009-07-02 07:28:31 +00:00
Evan Cheng 2c450d35ae Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
llvm-svn: 74692
2009-07-02 06:38:40 +00:00
David Goodwin 86c7e20ca6 Add PIC load and store patterns for Thumb-2.
llvm-svn: 74577
2009-07-01 00:01:13 +00:00
David Goodwin a83100f687 Thumb-2 load and store double description. But nothing yet creates them.
llvm-svn: 74566
2009-06-30 22:50:01 +00:00
David Goodwin d0890a2bad Add thumb-2 store word, halfword, and byte.
llvm-svn: 74555
2009-06-30 22:11:34 +00:00
David Goodwin 28d6d87244 Improve Thumb-2 jump table support.
llvm-svn: 74549
2009-06-30 19:50:22 +00:00
David Goodwin 27303cde82 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng 57726817aa A few more load instructions.
llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin 76b37950ca Add Thumb-2 support for TEQ amd TST.
llvm-svn: 74468
2009-06-29 22:49:42 +00:00
David Goodwin dbf11ba800 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng b23b50d54d Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
2009-06-29 07:51:04 +00:00