Commit Graph

175 Commits

Author SHA1 Message Date
Evan Cheng 7fae11b231 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Benjamin Kramer 1f97a5a671 Remove all remaining uses of Value::getNameStr().
llvm-svn: 144648
2011-11-15 16:27:03 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Jakob Stoklund Olesen 4f5f84c7e7 Teach antidependency breakers to use RegisterClassInfo.
No functional change was intended.

llvm-svn: 133202
2011-06-16 21:56:21 +00:00
Devang Patel f02a376fbc Update DBG_VALUEs while breaking anti dependencies.
llvm-svn: 132487
2011-06-02 21:26:52 +00:00
Andrew Trick 18c9b37a42 Add an issue width check to the postRA scheduler. Patch by Max Kazakov!
For targets with no itinerary (x86) it is a nop by default. For
targets with issue width already expressed in the itinerary (ARM) it
bypasses a scoreboard check but otherwise does not affect the
schedule. It does make the code more consistent and complete and
allows new targets to specify their issue width in an arbitrary way.

llvm-svn: 132385
2011-06-01 03:27:56 +00:00
Andrew Trick 84f9ad9bf2 Typo: Reviewed by Alistair.
llvm-svn: 131001
2011-05-06 18:14:32 +00:00
Andrew Trick aab77fe574 Post-RA scheduler compile time fix. Quadratic computation of DAG node depth.
The post-ra scheduler was explicitly updating the depth of a node's
successors after scheduling it, regardless of whether the successor
was ready. This is quadratic for DAGs with transitively redundant
edges. I simply removed the useless update of depth, which is lazilly
computed later.
Fixes <rdar://problem/9044332> compiler takes way too long to build TextInput.

llvm-svn: 130992
2011-05-06 17:09:08 +00:00
Andrew Trick 10ffc2b6c2 Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541
2010-12-24 05:03:26 +00:00
Evan Cheng bf4070756f Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570
2010-09-10 01:29:16 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Bill Wendling dd5e9d8faf Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.
llvm-svn: 108450
2010-07-15 20:01:02 +00:00
Evan Cheng 2d51c7c592 Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344
2010-06-18 23:09:54 +00:00
Evan Cheng 078f4cec21 - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.
- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.

llvm-svn: 105959
2010-06-14 21:06:53 +00:00
Evan Cheng e60273fd70 Allow target to provide its own hazard recognizer to post-ra scheduler.
llvm-svn: 105862
2010-06-12 00:12:18 +00:00
Evan Cheng 3858451e09 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
2010-05-21 20:53:24 +00:00
Jim Grosbach 63d4f68df4 Remove dbg_value workaround and associated command line option
llvm-svn: 104254
2010-05-20 18:34:01 +00:00
Jim Grosbach f98511473e Enable preserving debug information through post-RA scheduling
llvm-svn: 104175
2010-05-19 22:57:47 +00:00
Jim Grosbach d772bdeb7e 80 column and trailing whitespace cleanup
llvm-svn: 103806
2010-05-14 21:19:48 +00:00
Jim Grosbach 25749ad5c2 add cmd line option to leave dbgvalues in during post-RA sceduling. Useful
while debugging what's mishandled about them in the post-RA pass.

llvm-svn: 103805
2010-05-14 21:18:04 +00:00
Dan Gohman 25c1653700 Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.

llvm-svn: 102809
2010-05-01 00:01:06 +00:00
Bob Wilson 4e5eb5ae1b As a temporary workaround for post-RA not handling DebugValue instructions,
just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).

llvm-svn: 101604
2010-04-17 00:49:11 +00:00
Dan Gohman e4148978b8 Remove a #include.
llvm-svn: 101043
2010-04-12 16:26:03 +00:00
Dale Johannesen 2061c84109 Fix some more places where dbg_value affected codegen.
llvm-svn: 97765
2010-03-05 00:02:59 +00:00
David Greene aa8ce38113 Change errs() to dbgs().
llvm-svn: 92594
2010-01-05 01:26:01 +00:00
David Goodwin a45fe67667 <rdar://problem/7453528>. Track only physical registers that are valid for the target.
llvm-svn: 90970
2009-12-09 17:18:22 +00:00
Jakob Stoklund Olesen 8392456f1b Don't hang on to pointers or references after vector::push_back.
The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

llvm-svn: 90381
2009-12-03 01:49:56 +00:00
David Goodwin 80a03cc0b1 Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.
llvm-svn: 89471
2009-11-20 19:32:48 +00:00
David Goodwin b9fe5d5d02 Allow target to specify regclass for which antideps will only be broken along the critical path.
llvm-svn: 88682
2009-11-13 19:52:48 +00:00
David Goodwin da83f7d58b Rename registers to break output dependencies in addition to anti-dependencies.
llvm-svn: 87015
2009-11-12 19:08:21 +00:00
David Goodwin 0d412c2528 Fixed to address code review. No functional changes.
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
David Goodwin cf89db135e Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
llvm-svn: 86628
2009-11-10 00:15:47 +00:00
David Goodwin 7d8878add2 Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.
llvm-svn: 86098
2009-11-05 01:19:35 +00:00
David Goodwin 8501dbbe10 Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.
llvm-svn: 85939
2009-11-03 20:57:50 +00:00
Dan Gohman 34341e69c4 Make -print-machineinstrs more readable.
- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682
2009-10-31 20:19:03 +00:00
David Goodwin e30ed53c05 Make AntiDepReg.h internal.
llvm-svn: 85412
2009-10-28 18:29:54 +00:00
David Goodwin e056d1077e Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.
llvm-svn: 85166
2009-10-26 22:31:16 +00:00
David Goodwin 661ea989e9 Define virtual destructor in *.cpp file.
llvm-svn: 85146
2009-10-26 19:41:00 +00:00
David Goodwin de11f36ab7 Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
llvm-svn: 85145
2009-10-26 19:32:42 +00:00
David Goodwin 8370485db9 Break anti-dependence breaking out into its own class.
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
Nick Lewycky 974e12b2d3 Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Nick Lewycky 02d5f77d26 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
2009-10-25 06:33:48 +00:00
David Goodwin 02ad4cb32e Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
Dan Gohman 682a2d154a Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
llvm-svn: 84727
2009-10-21 01:44:44 +00:00
David Goodwin 4388beb884 Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.
llvm-svn: 84691
2009-10-20 22:50:43 +00:00
David Goodwin baf6dd26ea Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
llvm-svn: 84658
2009-10-20 19:54:44 +00:00
Evan Cheng 007ceb4603 Change createPostRAScheduler so it can be turned off at llc -O1.
llvm-svn: 84273
2009-10-16 21:06:15 +00:00
Evan Cheng 8b614768f8 If post-alloc scheduler is not enabled, it should return false, not true.
llvm-svn: 84248
2009-10-16 06:10:34 +00:00
David Goodwin 4c98efb917 Add debugging output.
llvm-svn: 84011
2009-10-13 19:16:03 +00:00
Dan Gohman 26e9b89b7c Fix a missing initialization of PostRAScheduler's AA member.
llvm-svn: 83695
2009-10-10 00:15:38 +00:00
Dan Gohman 87b02d5bbc Factor out LiveIntervalAnalysis' code to determine whether an instruction
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
2009-10-09 23:27:56 +00:00
Benjamin Kramer 3b008a3a65 Fix a use-after-free in post-ra-scheduling.
MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.

llvm-svn: 83249
2009-10-02 15:59:52 +00:00
David Goodwin d725159d9d All callee-saved registers are live-out of a return block.
llvm-svn: 83223
2009-10-01 23:28:47 +00:00
David Goodwin 1cc6dd97da Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
llvm-svn: 83218
2009-10-01 22:19:57 +00:00
David Goodwin 9a051a5922 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
llvm-svn: 83215
2009-10-01 21:46:35 +00:00
David Goodwin be3039e776 Use MachineFrameInfo.getPristineRegs() to determine which callee-saved registers are available for anti-dependency breaking. Some cleanup.
llvm-svn: 83208
2009-10-01 19:45:32 +00:00
Evan Cheng 4fb2891396 Observe hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. Do not change
operands of instructions with these properties while breaking anti-dep.

llvm-svn: 83198
2009-10-01 08:26:23 +00:00
Reid Kleckner 8ff5c19ebd Fix integer overflow in instruction scheduling. This can happen if we have
basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.

llvm-svn: 83159
2009-09-30 20:15:38 +00:00
David Goodwin 17199b56b0 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
llvm-svn: 83122
2009-09-30 00:10:16 +00:00
Jakob Stoklund Olesen 0bb5af345a Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.
llvm-svn: 83007
2009-09-28 20:32:46 +00:00
David Goodwin a4c98a3e34 Fix bug in kill flag updating for post-register-allocation scheduling. When the kill flag of a superreg needs to be cleared because there are one or more subregs live, we instead add implicit-defs of those subregs and leave the kill flag on the superreg. This allows us to end the live-range of the superreg without ending the live-ranges of the subregs.
llvm-svn: 82629
2009-09-23 16:35:25 +00:00
Evan Cheng 270d0f986f Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273
2009-09-18 21:02:19 +00:00
Benjamin Kramer e3c9d23bea It's a bool, so treat it like one. Fixes a MSVC warning.
llvm-svn: 81112
2009-09-06 12:10:17 +00:00
David Goodwin 6c08cfcfa0 Create our own block initializer for kill fixups as the scheduling one wasn't doing the right thing.
llvm-svn: 80958
2009-09-03 22:15:25 +00:00
David Goodwin 7f6516949b Add hidden flags to allow binary search of post-RA scheduling errors.
llvm-svn: 80702
2009-09-01 18:34:03 +00:00
David Goodwin c8985204d9 Don't mark a register live at an undef use.
llvm-svn: 80621
2009-08-31 20:47:02 +00:00
David Goodwin 7cb103dc8b Another stab at fixing up register kill flags after post-RA scheduling.
llvm-svn: 80410
2009-08-29 00:11:13 +00:00
David Goodwin ae6bc8214a Fixup register kills after scheduling.
llvm-svn: 80002
2009-08-25 17:03:05 +00:00
Chris Lattner 4883d90396 convert LoopInfo.h and GraphWriter.h to use raw_ostream
llvm-svn: 79836
2009-08-23 07:19:13 +00:00
David Goodwin 1f8c7a76f7 Fix counting of Post-RA scheduling stalls. Improve debug output.
llvm-svn: 78843
2009-08-12 21:47:46 +00:00
Dan Gohman 2a767c0d26 This logic was accidentally inverted in r78767.
llvm-svn: 78773
2009-08-12 01:44:20 +00:00
Dan Gohman f7912edba5 Factor out the code for finding an available register for use
in breaking an anti-dependence into a separate function.

llvm-svn: 78767
2009-08-12 01:33:27 +00:00
David Goodwin 92492f2f8e Use DEBUG macro for debug output.
llvm-svn: 78694
2009-08-11 17:56:42 +00:00
David Goodwin ebd694bb0a Add some debug output.
llvm-svn: 78687
2009-08-11 17:35:23 +00:00
David Goodwin f20236ac83 Replace DOUT.
llvm-svn: 78634
2009-08-11 01:44:26 +00:00
David Goodwin 6021b4dccc Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
llvm-svn: 78563
2009-08-10 15:55:25 +00:00
Dan Gohman 0402315d41 Use setPreservesAll and setPreservesCFG in CodeGen passes.
llvm-svn: 77754
2009-07-31 23:37:33 +00:00
Chris Lattner 7667332899 inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508
2009-07-29 21:36:49 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng 1ff2727c95 Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
llvm-svn: 70950
2009-05-05 00:30:09 +00:00
Bob Wilson 51856173c8 Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714
2009-04-09 17:16:43 +00:00
Duncan Sands be69d60d54 Add parentheses to pacify gcc-4.3.
llvm-svn: 66653
2009-03-11 09:04:34 +00:00
Dan Gohman 64613aceed Fix a post-RA scheduling liveness bug. When a basic block is being
scheduled in multiple regions, liveness data used by the
anti-dependence breaker is carried from one region to the next, however
the information reflects the state of the instructions before scheduling.
After scheduling, there may be new live range overlaps. Handle this by
pessimizing the liveness data carried between regions to the point where
it will be conservatively correct now matter how the earlier region is
scheduled. This fixes a miscompilation in 176.gcc with the post-RA
scheduler enabled.

llvm-svn: 66558
2009-03-10 18:10:43 +00:00
Dan Gohman dfaf646c34 When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.

Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.

llvm-svn: 64288
2009-02-11 04:27:20 +00:00
Dan Gohman b3dbb21df1 Consider any instruction that modifies the stack pointer to be
a scheduling region boundary.  This isn't necessary for
correctness; it helps with compile time, as it avoids the need
for data- and anti-dependencies from all spills and reloads on
the stack-pointer modification.

llvm-svn: 64255
2009-02-10 23:29:38 +00:00
Dan Gohman b95434356c Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across
scheduling regions. This fixes incorrect live-range information around
terminators and labels, which are effective region boundaries.

In place of looking for terminators to anchor inter-block dependencies,
introduce special entry and exit scheduling units for this purpose.

llvm-svn: 64254
2009-02-10 23:27:53 +00:00
Evan Cheng 066757eea1 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
llvm-svn: 63938
2009-02-06 17:43:24 +00:00
Dan Gohman f4b08b4f6c Move ScheduleDAGInstrs.h to be a private header. Front-ends
that used this header to select a scheduling policy should
use SchedulerRegistry.h instead (llvm-gcc and clang were
updated a while ago).

llvm-svn: 63934
2009-02-06 17:12:10 +00:00
Dan Gohman d564353193 Change the post-RA scheduler to iterate through the
basic-block segments bottom-up instead of top down. This
is the first step in a general restructuring of the way
register liveness is tracked in the post-RA scheduler.

llvm-svn: 63643
2009-02-03 18:57:45 +00:00
Dan Gohman 5f8a2598b2 Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.

Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.

llvm-svn: 62366
2009-01-16 22:10:20 +00:00
Dan Gohman 157e008816 If an anti-dependence uses a non-allocatable register, set AntiDepReg
to 0, to ensure that the subsequent code doesn't try to break the
dependence.

llvm-svn: 62365
2009-01-16 21:57:43 +00:00
Dan Gohman 014142fd1a Fix the check for an empty basic block to check for an empty SUnits
array instead, since this is what the scheduler actually cares about.
And remove a check that is unnecessary, since it can assume that
SUnits isn't empty.

llvm-svn: 62362
2009-01-16 21:37:14 +00:00
Dan Gohman b903071735 Fix a "comparison between signed and unsigned integer expressions"
warning.

llvm-svn: 62327
2009-01-16 17:55:08 +00:00
Dan Gohman ceac7c34f1 Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.

llvm-svn: 62291
2009-01-16 01:33:36 +00:00
Dan Gohman 619ef48a52 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
2009-01-15 19:20:50 +00:00
Dan Gohman 906152a20f Tidy up #includes, deleting a bunch of unnecessary #includes.
llvm-svn: 61715
2009-01-05 17:59:02 +00:00