llvm-project

Commit Graph

Author	SHA1	Message	Date
Benjamin Kramer	729d361834	[tblgen] Compare const char * with strcmp instead of creating StringRef. Avoids a call to strlen on both strings which always reads the entire string. strcmp can use early exit. llvm-svn: 276737	2016-07-26 09:27:51 +00:00
Tim Northover	be22e5ccbe	TableGen: avoid string copy. llvm-svn: 274584	2016-07-05 22:51:30 +00:00
Tim Northover	e6ae6767d9	AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576	2016-07-05 21:23:04 +00:00

Author

SHA1

Message

Date

Benjamin Kramer

729d361834

[tblgen] Compare const char * with strcmp instead of creating StringRef.

Avoids a call to strlen on both strings which always reads the entire
string. strcmp can use early exit.

llvm-svn: 276737

2016-07-26 09:27:51 +00:00

Tim Northover

be22e5ccbe

TableGen: avoid string copy.

llvm-svn: 274584

2016-07-05 22:51:30 +00:00

Tim Northover

e6ae6767d9

AArch64: TableGenerate system instruction operands.

The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

llvm-svn: 274576

2016-07-05 21:23:04 +00:00

3 Commits