3277557741
Update comment.
...
llvm-svn: 145866
2011-12-05 22:53:09 +00:00
19446a07a7
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
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where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
llvm-svn: 145865
2011-12-05 22:37:00 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
e489babf9b
Thumb2 prefer ADD register encoding T2 to T3 when possible.
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rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
9b8ac674bc
Split ExtIns into two base classes and have instructions EXT and INS derive from
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them.
llvm-svn: 145852
2011-12-05 21:14:28 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
9e90c5cde3
Fix previous commit. Oops.
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llvm-svn: 145844
2011-12-05 20:12:26 +00:00
2b37e4fc80
Tidy up. No functional change.
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llvm-svn: 145843
2011-12-05 20:09:44 +00:00
0a978ef715
ARM assmebler parsing for two-operand VMUL instructions.
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Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
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llvm-svn: 145819
2011-12-05 17:55:17 +00:00
72a26e8b8d
don't include CR bit subregs in callee-saved list
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llvm-svn: 145818
2011-12-05 17:55:12 +00:00
b544019a60
add register pressure for CR regs
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llvm-svn: 145816
2011-12-05 17:54:17 +00:00
13231037f0
Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks.
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- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.
llvm-svn: 145810
2011-12-05 17:23:27 +00:00
51bec1a37a
Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions.
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llvm-svn: 145804
2011-12-05 07:27:14 +00:00
6a55b1dd9f
Clean up and optimizations to the X86 shuffle lowering code. No functional change.
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llvm-svn: 145803
2011-12-05 06:56:46 +00:00
3924cb0267
Add support for vectors of pointers.
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llvm-svn: 145801
2011-12-05 06:29:09 +00:00
8dda5d0f06
Add inline subprogram names to the name lookup table since they may
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not get there any other way.
llvm-svn: 145789
2011-12-04 06:02:38 +00:00
80381f6cbf
Fix 80-column issues.
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llvm-svn: 145783
2011-12-04 00:52:23 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
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AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
71ba18c1e0
Simplify code. No functionality change.
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-3% on ARMDissasembler.cpp.
llvm-svn: 145773
2011-12-03 16:18:22 +00:00
bbf3c60786
Clear the new cache.
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llvm-svn: 145771
2011-12-03 15:19:55 +00:00
3664708378
Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps.
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-15% on ARMDisassembler.cpp (Release build). It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.
llvm-svn: 145770
2011-12-03 15:16:45 +00:00
006e43bcc0
Check for stack space more intelligently.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
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Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
8fd1254a0a
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
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the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
llvm-svn: 145745
2011-12-03 02:45:50 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
e03fe83d98
Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur
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Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
llvm-svn: 145731
2011-12-03 00:04:30 +00:00
0155a63513
Add support for constant folding the pow intrinsic.
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rdar://10514247
llvm-svn: 145730
2011-12-03 00:00:03 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
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llvm-svn: 145726
2011-12-02 23:34:39 +00:00
2635f54cb6
ARM VEXT tighten up operand classes a bit.
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llvm-svn: 145722
2011-12-02 22:57:57 +00:00
eb53822f5a
ARM VST1 single lane assembly parsing.
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llvm-svn: 145718
2011-12-02 22:34:51 +00:00
50f02cb21b
Move global variables in TargetMachine into new TargetOptions class. As an API
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change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
llvm-svn: 145714
2011-12-02 22:16:29 +00:00
dda976b804
ARM VLD1 single lane assembly parsing.
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llvm-svn: 145712
2011-12-02 22:01:52 +00:00
81c9003695
ARM encoder method needs the physical register number, not the enum.
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llvm-svn: 145711
2011-12-02 22:01:25 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
4d2b871cda
Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller.
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The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.
llvm-svn: 145690
2011-12-02 18:37:31 +00:00
bccc4c17f3
Check for error after InstantiateMultclassDef.
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llvm-svn: 145689
2011-12-02 18:33:03 +00:00
1280eb1d06
Add XOP feature flag.
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llvm-svn: 145682
2011-12-02 15:14:37 +00:00
b67440367f
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
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llvm-svn: 145681
2011-12-02 08:18:41 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
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llvm-svn: 145680
2011-12-02 07:16:01 +00:00
f9ce7b60ef
remove unneeded FIXME comment
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llvm-svn: 145679
2011-12-02 04:58:17 +00:00
4201820275
make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop
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llvm-svn: 145677
2011-12-02 04:58:07 +00:00
58ca360081
update PPC 940 hazard rec. to function in postRA mode
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llvm-svn: 145676
2011-12-02 04:58:02 +00:00
43a33066b4
Fix a few more places where TargetData/TargetLibraryInfo is not being passed.
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Add FIXMEs to places that are non-trivial to fix.
llvm-svn: 145661
2011-12-02 01:26:24 +00:00
04945c42c6
ARM start parsing VLD1 single lane instructions.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
576c0f8e54
Abuse of mass replace isn't warranted even when the build is failing. Thanks
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for the suggestion, Eric.
llvm-svn: 145643
2011-12-01 23:16:03 +00:00
54a506dcb1
Fix build by not assuming TLI is guaranteed. Will have to track down cases where
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TLI isn't being passed to ensure we don't miss opportunities to fold calls.
llvm-svn: 145641
2011-12-01 22:38:31 +00:00
3367123b12
Prevent library calls from being folded if -fno-builtin has been specified.
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rdar://10500969
llvm-svn: 145639
2011-12-01 22:14:50 +00:00
c19f0b7357
CodeGen: fix CMake build
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Missing file from r145629.
llvm-svn: 145634
2011-12-01 21:49:23 +00:00
19a58df9bb
ExecutionEngine: honor optimization level
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It was getting ignored after r144788.
Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.
llvm-svn: 145633
2011-12-01 21:49:21 +00:00
e6de63dfc5
Last bit of TargetLibraryInfo propagation. Also fixed a case for TargetData
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where it appeared beneficial to pass.
More of rdar://10500969
llvm-svn: 145630
2011-12-01 21:29:16 +00:00
08ebdc1e71
Add a deterministic finite automaton based packetizer for VLIW architectures
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llvm-svn: 145629
2011-12-01 21:10:21 +00:00
54c9462c77
Fix unreachable return & simplify some branches.
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llvm-svn: 145627
2011-12-01 20:58:30 +00:00
f60485c4cf
Dummy commit to check commit access.
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llvm-svn: 145619
2011-12-01 19:15:08 +00:00
fdddc27143
Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment
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llvm-svn: 145618
2011-12-01 19:13:26 +00:00
d594bac68b
[asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found
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llvm-svn: 145611
2011-12-01 18:54:53 +00:00
676c093758
Add missing functions.
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llvm-svn: 145608
2011-12-01 18:26:19 +00:00
3ced545ccf
Autodetect bulldozers.
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llvm-svn: 145607
2011-12-01 18:24:17 +00:00
10fe1fe39e
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
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llvm-svn: 145596
2011-12-01 17:54:37 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
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sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
3a15e14520
Add some missing anchors.
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llvm-svn: 145578
2011-12-01 08:00:17 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
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llvm-svn: 145573
2011-12-01 04:49:21 +00:00
bc5c524b71
Added instcombine pattern to spot comparing -val or val against 0.
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(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"
Fixes <rdar://problem/10482509>
llvm-svn: 145563
2011-12-01 03:58:40 +00:00
c24b86ffbe
Propagate TargetLibraryInfo throughout ConstantFolding.cpp and
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InstructionSimplify.cpp. Other fixups as needed.
Part of rdar://10500969
llvm-svn: 145559
2011-12-01 03:08:23 +00:00
e659b8459e
Make use of "getScalarType()". No functionality change.
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llvm-svn: 145556
2011-12-01 02:39:36 +00:00
c1870b2633
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
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llvm-svn: 145553
2011-12-01 01:43:47 +00:00
dc436f95d2
make asan work at -O0, llvm part. Patch by glider@google.com
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llvm-svn: 145530
2011-11-30 22:19:26 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
...
remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
6cff9df298
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
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<rdar://problem/10497732>.
llvm-svn: 145523
2011-11-30 21:54:15 +00:00
23c30b90e3
Remove unused variable
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llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
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llvm-svn: 145510
2011-11-30 19:35:44 +00:00
738da252ab
Add a few functions to TargetLibraryInfo.
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llvm-svn: 145508
2011-11-30 19:19:00 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
5feb3dab79
X86: Turns out bulldozer also supports sse42 and lzcnt.
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While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
llvm-svn: 145494
2011-11-30 15:48:16 +00:00
981f32327d
X86: Add subtargets for AMD's bulldozer.
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llvm-svn: 145493
2011-11-30 15:27:46 +00:00
96923cc2bb
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
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llvm-svn: 145488
2011-11-30 10:13:37 +00:00
c4977ba413
Add instruction selection support for AVX2 horizontal add/sub instructions.
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llvm-svn: 145487
2011-11-30 09:10:50 +00:00
0a672eaf9e
Merge VPERM2F128/VPERM2I128 ISD node types.
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llvm-svn: 145485
2011-11-30 07:47:51 +00:00
bafd224c8b
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
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llvm-svn: 145483
2011-11-30 06:25:25 +00:00
ceafa2c746
LSR: handle the expansion of phi operands that use postinc forms of the IV.
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Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.
llvm-svn: 145482
2011-11-30 06:07:54 +00:00
385d9f6c24
Whitespace.
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llvm-svn: 145470
2011-11-30 01:59:59 +00:00
abba0947db
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
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change intended.
llvm-svn: 145468
2011-11-30 01:51:49 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
82e1bd8e94
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
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(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
llvm-svn: 145460
2011-11-29 23:57:10 +00:00
182b6a077e
Tidy up a bit.
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llvm-svn: 145458
2011-11-29 23:51:09 +00:00
ae672f8118
Add comment.
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llvm-svn: 145456
2011-11-29 23:33:40 +00:00
e1154eef0b
ARM parsing aliases for data-size suffices on VST1.
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llvm-svn: 145454
2011-11-29 23:21:31 +00:00
dc25f9f38a
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
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llvm-svn: 145450
2011-11-29 22:58:48 +00:00
648e48d02e
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
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llvm-svn: 145448
2011-11-29 22:48:34 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
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llvm-svn: 145442
2011-11-29 22:38:04 +00:00
bde32d36bb
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
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Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
llvm-svn: 145440
2011-11-29 22:27:25 +00:00
31798ef3c0
Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop.
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llvm-svn: 145432
2011-11-29 20:34:39 +00:00
46addb9e07
If fast-isel fails, remove dead instructions generated during the failed
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attempt.
llvm-svn: 145425
2011-11-29 19:40:47 +00:00
312b97c267
comment.
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llvm-svn: 145422
2011-11-29 19:33:49 +00:00
Chad Rosier