698e84fc4f
Remove the Function::getFnAttributes method in favor of using the AttributeSet
...
directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
llvm-svn: 171253
2012-12-30 10:32:01 +00:00
6190254e0f
s/hasAttribute/contains/g to be more consistent with other method names.
...
llvm-svn: 171252
2012-12-30 09:17:46 +00:00
0b37f14371
LoopVectorizer: Fix a bug in the code that updates the loop exiting block.
...
LCSSA PHIs may have undef values. The vectorizer updates values that are used by outside users such as PHIs.
The bug happened because undefs are not loop values. This patch handles these PHIs.
PR14725
llvm-svn: 171251
2012-12-30 07:47:00 +00:00
56bf2e1830
Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID
...
This is done to avoid odd test failures, like the one fixed in r171243.
llvm-svn: 171250
2012-12-30 02:33:22 +00:00
3a554ac065
Add a few more c'tors:
...
* One that accepts a single Attribute::AttrKind.
* One that accepts an Attribute::AttrKind plus a list of values. This is for
attributes defined like this:
#1 = attributes { align = 4 }
* One that accepts a string, for target-specific attributes like this:
#2 = attributes { "cpu=cortex-a8" }
llvm-svn: 171249
2012-12-30 02:22:16 +00:00
10c4b4d249
Add a check to the test Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll
...
This test did not test anything at all (except for opt crashing, but that was
not the reason why it was added).
llvm-svn: 171248
2012-12-30 01:42:34 +00:00
b1d12619c9
Add a few (as yet unused) query methods to determine if the attribute that's
...
stored here is of a certain kind. This is in preparation for when an Attribute
object represents a single attribute, instead of a bitmask of attributes.
llvm-svn: 171247
2012-12-30 01:38:39 +00:00
b137c9e551
Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID
...
This is done to avoid odd test failures, like the one fixed in r171243.
llvm-svn: 171246
2012-12-30 01:28:40 +00:00
5e8ff877f4
Uniquify the AttributeImpl based on the Constant pointer, since those are
...
already uniquified.
Note: This will be expanded in the future to add more than just one pointer
value.
llvm-svn: 171245
2012-12-30 01:23:08 +00:00
3e4c4c9607
s/Raw/getBitMask/g to be more in line with current naming conventions. This method won't be sticking around.
...
llvm-svn: 171244
2012-12-30 01:05:42 +00:00
5a495a5c96
llvm/test/Transforms/GVN/null-aliases-nothing.ll: Fix a RUN line not to emit ModuleID.
...
Larry Evans reported it fails if source tree contains "load", like "download".
llvm-svn: 171243
2012-12-30 00:33:26 +00:00
fe82eb6bcd
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
...
llvm-svn: 171237
2012-12-29 18:18:20 +00:00
f4a9c6e21b
Merge similar functionality using a nested switch.
...
llvm-svn: 171229
2012-12-29 17:19:06 +00:00
6b27251a76
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
...
llvm-svn: 171227
2012-12-29 16:44:25 +00:00
215f94143c
Simplify code, no functionality change.
...
llvm-svn: 171226
2012-12-29 15:57:26 +00:00
afe8109fce
Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.
...
llvm-svn: 171225
2012-12-29 15:23:06 +00:00
0cd0f7f832
Use a 'Constant' object instead of a bit field to store the attribute data.
...
llvm-svn: 171221
2012-12-29 12:29:38 +00:00
4fdde84613
Use the accessor method instead of the raw ivar to get the bits.
...
llvm-svn: 171220
2012-12-29 12:10:46 +00:00
405d681340
Nuke some dead code that snuck in some how. I thought I had already
...
deleted this, but apparantly not. Charmingly, Clang didn't warn on it
but GCC did.
llvm-svn: 171197
2012-12-28 14:50:51 +00:00
86ed53089f
Fix a stunning oversight in the inline cost analysis. It was never
...
propagating one of the values it simplified to a constant across
a myriad of instructions. Notably, ptrtoint instructions when we had
a constant pointer (say, 0) didn't propagate that, blocking a massive
number of down-stream optimizations.
This was uncovered when investigating why we fail to inline and delete
the boilerplate in:
void f() {
std::vector<int> v;
v.push_back(1);
}
It turns out most of the efforts I've made thus far to improve the
analysis weren't making it far purely because of this. After this is
fixed, the store-to-load forwarding patch enables LLVM to optimize the
above to an empty function. We still can't nuke a second push_back, but
for different reasons.
There is a very real chance this will cause somewhat noticable changes
in inlining behavior, so please let me know if you see regressions (or
improvements!) because of this patch.
llvm-svn: 171196
2012-12-28 14:43:42 +00:00
753e21d057
Teach the inline cost analysis about calls that can be simplified and
...
how to propagate constants through insert and extract value
instructions.
With the recent improvements to instsimplify, this allows inline cost
analysis to constant fold through intrinsic functions, including notably
the with.overflow intrinsic math routines which often show up inside of
STL abstractions. This is yet another piece in the puzzle of breaking
down the code for:
void f() {
std::vector<int> v;
v.push_back(1);
}
But it still isn't enough. There are a pile of bugs in inline cost still
blocking this.
llvm-svn: 171195
2012-12-28 14:23:32 +00:00
f6182155f6
Teach instsimplify to use the constant folder where appropriate for
...
constant folding calls. Add the initial tests for this which show that
now instsimplify can simplify blindingly obvious code patterns expressed
with both intrinsics and library calls.
llvm-svn: 171194
2012-12-28 14:23:29 +00:00
9dc3558920
Add entry points to instsimplify for simplifying calls. The entry points
...
are nice and decomposed so that we can simplify synthesized calls as
easily as actually call instructions. The internal utility still has the
same behavior, it just now operates on a more generic interface so that
I can extend the set of call simplifications that instsimplify knows
about.
llvm-svn: 171189
2012-12-28 11:30:55 +00:00
3efc87e92d
Add proper support for -fsanitize-blacklist= flag for TSan and MSan. LLVM part.
...
llvm-svn: 171183
2012-12-28 09:30:44 +00:00
9785f519b4
CostModel: initial checkin for code that estimates the cost of special shuffles.
...
llvm-svn: 171180
2012-12-28 08:19:03 +00:00
c982a2dc25
wrap 80-col lines.
...
llvm-svn: 171179
2012-12-28 07:28:43 +00:00
3da9ac72fa
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
...
llvm-svn: 171178
2012-12-28 05:45:24 +00:00
68441914a5
Reverse the 'if' condition and reduce the indentation.
...
llvm-svn: 171172
2012-12-27 23:08:05 +00:00
ab2e6842cc
Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.
...
llvm-svn: 171171
2012-12-27 22:53:47 +00:00
3b34190100
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
...
llvm-svn: 171170
2012-12-27 22:47:16 +00:00
e2eec3c52b
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
...
llvm-svn: 171166
2012-12-27 18:51:50 +00:00
3edd52c1d0
Add support to BasicBlocks for iterating backwards over the
...
instructions. This just exposes the already present reverse iterators of
the instruction ilist.
llvm-svn: 171159
2012-12-27 12:00:56 +00:00
a3c0d67d5b
Provide a common half-open interval map info implementation, and just
...
re-use that for SlotIndexes. This way other users who want half-open
semantics can share the implementation.
llvm-svn: 171158
2012-12-27 11:29:17 +00:00
e40e60eed5
Make this parameter be named consistently with most other
...
getAnalysisUsage implementations.
llvm-svn: 171157
2012-12-27 11:17:15 +00:00
0f2eabce10
docs: Add FAQ about "storing to a virtual register".
...
This came up for the N+1'st time today in IRC.
llvm-svn: 171155
2012-12-27 10:23:04 +00:00
33fc6cff4b
docs: Move link to the new "external tutorials" area.
...
llvm-svn: 171154
2012-12-27 08:57:08 +00:00
29dd7f2090
[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments
...
llvm-svn: 171153
2012-12-27 08:50:58 +00:00
9aa00f0363
DAGCombinerInformation: add a getter that exposes the dagcombine level.
...
llvm-svn: 171152
2012-12-27 08:44:35 +00:00
75ceb5b56b
Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer
...
llvm-svn: 171150
2012-12-27 08:40:37 +00:00
f85d3ee072
docs: Update the benchmark with updated perf numbers.
...
llvm-svn: 171149
2012-12-27 08:32:44 +00:00
2a054b4475
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
...
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
llvm-svn: 171148
2012-12-27 08:15:45 +00:00
8e5d80eba3
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
...
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
llvm-svn: 171146
2012-12-27 07:45:10 +00:00
757f3fc394
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
...
llvm-svn: 171143
2012-12-27 07:16:08 +00:00
b1dd52450e
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
...
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase.
llvm-svn: 171142
2012-12-27 06:47:41 +00:00
09ce4b9efe
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
...
llvm-svn: 171141
2012-12-27 06:34:54 +00:00
8f0b73942e
Update tablegen parser to allow defm names to start with #NAME.
...
llvm-svn: 171140
2012-12-27 06:32:52 +00:00
396cb795bc
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
...
llvm-svn: 171137
2012-12-27 03:35:44 +00:00
c7910828e4
Mark the divide instructions as hasSideEffects=0.
...
llvm-svn: 171136
2012-12-27 03:01:18 +00:00
3bf29fda91
For the dwarf5 split debug info code split out the string section
...
per compile unit/skeleton compile unit. Update tests accordingly.
llvm-svn: 171133
2012-12-27 02:14:01 +00:00
c8a88ee691
FileCheck-ize.
...
llvm-svn: 171132
2012-12-27 02:13:58 +00:00
d6152aabbb
FileCheck-ize.
...
llvm-svn: 171131
2012-12-27 02:13:55 +00:00
5b807aaa38
Add hasSideEffects=0 to CMP*rr_REV.
...
llvm-svn: 171130
2012-12-27 02:08:46 +00:00
b3f6751df5
whitespace
...
llvm-svn: 171129
2012-12-27 02:04:12 +00:00
89e8607755
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
...
llvm-svn: 171128
2012-12-27 02:01:33 +00:00
5a6acfa4c8
Right now all of the relocations are 32-bit dwarf, and the relocation
...
information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.
llvm-svn: 171126
2012-12-27 01:07:07 +00:00
5350cd314b
If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified.
...
PR14719.
llvm-svn: 171124
2012-12-26 23:30:53 +00:00
c557343956
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
...
llvm-svn: 171123
2012-12-26 23:27:57 +00:00
d47a70de9f
Add hasSideEffects=0 to some atomic instructions.
...
llvm-svn: 171122
2012-12-26 23:08:12 +00:00
af2372087b
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
...
llvm-svn: 171121
2012-12-26 22:19:23 +00:00
fca2acb618
80 columns. No functionality change.
...
llvm-svn: 171120
2012-12-26 22:00:49 +00:00
90053a1214
Remove mid-optimizer warning. This situation should be handled differently,
...
such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.
llvm-svn: 171119
2012-12-26 22:00:35 +00:00
1b8c0750ee
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
...
llvm-svn: 171118
2012-12-26 21:30:22 +00:00
18f2675e9b
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
...
llvm-svn: 171117
2012-12-26 21:04:30 +00:00
0bbf81e311
Update the docs with the new workload that was added.
...
llvm-svn: 171115
2012-12-26 19:45:00 +00:00
3f7c4f36ba
LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1
...
llvm-svn: 171114
2012-12-26 19:08:17 +00:00
8d5f8dc485
Fix comment typo
...
llvm-svn: 171113
2012-12-26 18:15:42 +00:00
5eb5bf8b46
[msan] Raise alignment of origin stores/loads when possible.
...
Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.
llvm-svn: 171110
2012-12-26 11:55:09 +00:00
d8be0c510c
[msan] Expand the file comment with track-origins info.
...
llvm-svn: 171109
2012-12-26 10:59:00 +00:00
d14720dced
Fix quoting in configure. Patch by Krzysztof Parzyszek!
...
llvm-svn: 171108
2012-12-26 10:48:49 +00:00
24f316e4db
Merge still more SSE/AVX instruction definitions.
...
llvm-svn: 171103
2012-12-26 07:54:43 +00:00
af629e2700
Merge more SSE/AVX instruction definitions.
...
llvm-svn: 171102
2012-12-26 07:20:35 +00:00
bf99a426cb
TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction().
...
Reported by Yang Yongyong, thanks!
llvm-svn: 171101
2012-12-26 06:43:14 +00:00
a1d2436b5f
revert an accidental commit.
...
llvm-svn: 171098
2012-12-26 06:16:03 +00:00
65fe30450d
Fix 80 column violation.
...
llvm-svn: 171097
2012-12-26 06:15:53 +00:00
f4d0fe8fcd
Fix class name in comment.
...
llvm-svn: 171096
2012-12-26 06:15:09 +00:00
59747c4dbd
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
...
llvm-svn: 171095
2012-12-26 06:14:15 +00:00
7375d35711
Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel.
...
llvm-svn: 171094
2012-12-26 06:03:35 +00:00
8a48677586
Remove 'v' from mnemonic to fix asm matching failures.
...
llvm-svn: 171093
2012-12-26 06:02:15 +00:00
b4ef0fa3a1
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
...
llvm-svn: 171092
2012-12-26 05:49:15 +00:00
5267bb71b8
Reformat the docs.
...
llvm-svn: 171091
2012-12-26 04:59:20 +00:00
0e1d662d56
white space
...
llvm-svn: 171090
2012-12-26 04:58:12 +00:00
a2594dd5f0
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN
...
llvm-svn: 171087
2012-12-26 04:36:03 +00:00
97730a0d6a
Merge an AVX/SSE 256-bit and 128-bit multiclass.
...
llvm-svn: 171086
2012-12-26 03:56:47 +00:00
8b59746390
Mark VANDNPD/VANDNPDS as not commutable.
...
llvm-svn: 171085
2012-12-26 03:48:10 +00:00
40aa3285f4
llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083.
...
llvm-svn: 171084
2012-12-26 03:19:30 +00:00
334f685328
llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082.
...
llvm-svn: 171083
2012-12-26 03:08:55 +00:00
81d1e596bb
Remove alignment from a bunch more VEX encoded operations in the folding tables.
...
llvm-svn: 171082
2012-12-26 02:44:47 +00:00
b2922164f0
Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...
...
llvm-svn: 171081
2012-12-26 02:14:19 +00:00
d09a9af9b6
Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.
...
llvm-svn: 171080
2012-12-26 01:47:12 +00:00
30e95a8ebb
BBVectorize: Use VTTI to compute costs for intrinsics vectorization
...
For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.
Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.
llvm-svn: 171079
2012-12-26 01:36:57 +00:00
caef1c5d86
Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.
...
llvm-svn: 171078
2012-12-26 00:35:47 +00:00
b44f890133
LoopVectorize: Enable vectorization of the fmuladd intrinsic
...
llvm-svn: 171076
2012-12-25 23:21:29 +00:00
2a456112ec
BBVectorize: Enable vectorization of the fmuladd intrinsic
...
llvm-svn: 171075
2012-12-25 22:36:08 +00:00
2ebe6d08cd
Loosen scheduling restrictions on the PPC dcbt intrinsic
...
As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.
llvm-svn: 171073
2012-12-25 18:51:18 +00:00
1b5ff08d43
Expand PPC64 atomic load and store
...
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
llvm-svn: 171072
2012-12-25 17:22:53 +00:00
f19c086d1e
[msan] Fix handling of vectors of pointers.
...
VectorType::getInteger() can not be used with them, because pointer size
depends on the target.
llvm-svn: 171070
2012-12-25 16:04:38 +00:00
ec8371283b
[msan] Fix handling of select with vector condition.
...
llvm-svn: 171069
2012-12-25 14:56:21 +00:00
a9f265ee98
Harden test so it's not affected by changes to compare lowering.
...
This only failed on hosts that don't have SSE41.
llvm-svn: 171066
2012-12-25 13:23:23 +00:00
81b5a8fd2e
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
...
llvm-svn: 171064
2012-12-25 13:09:08 +00:00
df4af41b9b
X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.
...
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).
llvm-svn: 171063
2012-12-25 12:54:19 +00:00
Bill Wendling