This is meant to cover cases such as the obvious
Base *base = new Derived();
where GetDynamicTypeAndAddress(base) would return the type "Derived", not "Derived *"
llvm-svn: 248315
Summary:
`TypeTraitExpr`s are not supported by the ExprEngine today. Analyzer
creates a sink, and aborts the block. Therefore, certain bugs that
involve type traits intrinsics cannot be detected (see PR24710).
This patch creates boolean `SVal`s for `TypeTraitExpr`s, which are
evaluated by the compiler.
Test within the patch is a summary of PR24710.
Reviewers: zaks.anna, dcoughlin, krememek
Subscribers: cfe-commits
Differential Revision: http://reviews.llvm.org/D12482
llvm-svn: 248314
Summary:
In rL241532, atomic_support.h was added, which provides handling of
atomic operations for libc++. When atomic builtins are not available,
it emits a warning about being unsupported, but it still provides a
number of stubs for the required functions.
However, it misses a stub for `__libcpp_relaxed_store()`. Add it, by
using the same implementation as for `__libcpp_atomic_store()`.
(Note that I encountered this on arm-freebsd, which still defaults to
armv4, and does not have the runtime libcalls to support atomic
builtins. For now, I have simply disabled using them.)
Reviewers: mclow.lists, EricWF
Subscribers: theraven, cfe-commits, jroelofs, majnemer, aemerson
Differential Revision: http://reviews.llvm.org/D13051
llvm-svn: 248313
This is just enough to get PLT working on 32 bit x86.
The idea behind using a virtual interface is that it should be easy to
convert any of the functions to template parameters if any turns out to be
performance critical.
llvm-svn: 248308
* adds -aux-triple option to specify target triple
* propagates aux target info to AST context and Preprocessor
* pulls in target specific preprocessor macros.
* pulls in target-specific builtins from aux target.
* sets appropriate host or device attribute on builtins.
Differential Revision: http://reviews.llvm.org/D12917
llvm-svn: 248299
* Only the last of the --cuda-host-only/--cuda-device-only options has effect.
* CudaHostAction always wraps host-side compilation now.
* Fixed printing of empty action lists.
Differential Revision: http://reviews.llvm.org/D12892
llvm-svn: 248297
The changes are part of attribute-based CUDA function overloading (D12453)
and as such are only enabled when it's in effect (-fcuda-target-overloads).
Differential Revision: http://reviews.llvm.org/D12122
llvm-svn: 248296
The patch makes it possible to parse CUDA files that contain host/device
functions with identical signatures, but different attributes without
having to physically split source into host-only and device-only parts.
This change is needed in order to parse CUDA header files that have
a lot of name clashes with standard include files.
Gory details are in design doc here: https://goo.gl/EXnymm
Feel free to leave comments there or in this review thread.
This feature is controlled with CC1 option -fcuda-target-overloads
and is disabled by default.
Differential Revision: http://reviews.llvm.org/D12453
llvm-svn: 248295
ARM counterpart to r248291:
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.
Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.
Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".
Differential Revision: http://reviews.llvm.org/D13033
llvm-svn: 248294
This makes sure that we emit kernels that were instantiated from the
host code and which would never be explicitly referenced by anything
else on device side.
Differential Revision: http://reviews.llvm.org/D11666
llvm-svn: 248293
This is useful for debugging of issues and reduction of test cases.
For example, an issue may show up due to the order that some commands were processed.
It is convenient to be able to remove commands from the file and still preserve the order
that they are returned, instead of getting a completely different order when removing a few commands.
llvm-svn: 248292
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.
Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.
Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".
Differential Revision: http://reviews.llvm.org/D13033
llvm-svn: 248291
Summary:
This is no longer related to Clang and is just an opaque pointer
to data for a compiler type.
Reviewers: clayborg
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D13039
llvm-svn: 248288
Summary:
The corresponding .cpp file was removed in September of 2011 in
r139772.
Reviewers: spyffe, clayborg
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D13043
llvm-svn: 248286
I'm seeing timed out tests not properly timing out on the Linux
build bot after this change. Not sure if it is related but
seems suspect.
llvm-svn: 248284
Summary:
pthread_setname_np() is a nonstandard GNU extension and isn't available
in every C library. Check before it's usage that GLIBC is available or
that we are targeting Android.
Reviewers: clayborg, ovyalov
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D13019
llvm-svn: 248280
After the std::move operation the unique pointer is null.
So this statement always returns a null pointer.
Also remove unnecessary call to Module::ParseAllDebugSymbols(),
which spews errors due to how it incorrectly tries to parse DWARF DIE types.
llvm-svn: 248274
Summary:
Almost no functional change since the InstrItinData's have been duplicated.
The one functional change is to remove IIBranch from the MSA branches. The
classes will be assigned to the MSA instructions as part of implementing
the P5600 scheduler.
II_IndirectBranchPseudo and II_ReturnPseudo can probably be removed. I've
preserved the itinerary information for the corresponding pseudo
instructions to avoid making a functional change to these pseudos in
this patch.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12189
llvm-svn: 248273
These two tests are skipped on Linux with a comment that the behaviour
is as expected, but they are consistently passing on FreeBSD now.
llvm.org/pr15989
llvm-svn: 248271
Summary:
The only instructions left in IIAlu are MIPS16 specific. We're not
implementing a MIPS16 scheduler at this time so rename the class to make it
obvious that they are MIPS16 instructions.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D12188
llvm-svn: 248267
Enrico Granata