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5 Commits

Author SHA1 Message Date
David Green eecba95067 [ARM] Replace arm vendor with none. NFC 2020-04-22 18:19:35 +01:00
David Green b535aa405a [ARM] Use reduction intrinsics for larger than legal reductions 
The codegen for splitting a llvm.vector.reduction intrinsic into parts
will be better than the codegen for the generic reductions. This will
only directly effect when vectorization factors are specified by the
user.

Also added tests to make sure the codegen for larger reductions is OK.

Differential Revision: https://reviews.llvm.org/D72257
 2020-01-24 17:07:24 +00:00
Sam Tebbs a69d9d6156 Reapply: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32 
The CodeGen/Thumb2/mve-vaddv.ll test needed to be amended to reflect the
changes from the above patch.

This reverts commit cd53ff6, reapplying 7c6b229.

llvm-svn: 369638
 2019-08-22 10:29:20 +00:00
Sam Tebbs dcfc2d40d3 [ARM] Select vaddva 
This patch adds vaddva selection.

Differential revision: https://reviews.llvm.org/D66410

llvm-svn: 369404
 2019-08-20 16:33:34 +00:00
Sam Tebbs f312c1ecf4 [ARM] Add support for MVE vaddv 
This patch adds vecreduce_add and the relevant instruction selection for
vaddv.

Differential revision: https://reviews.llvm.org/D66085

llvm-svn: 369245
 2019-08-19 09:38:28 +00:00