4 Commits

Author	SHA1	Message	Date
Fangrui Song	1f333562de	[PowerPC] Support constraint code "ww" ... Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106	2019-07-04 04:44:42 +00:00
Dmitri Gribenko	3d0576bbaf	Fixed a typo in the test s/CEHCK/CHECK/ ... Summary: Turns out the test was not correct, I had to adjust the test to work. I also added CHECK-LABELs for better error messages from FileCheck while I'm here. Reviewers: jsji Subscribers: nemanjai, eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58614 llvm-svn: 355079	2019-02-28 10:56:39 +00:00
Li Jia He	03170a904f	[PowerPC] Support constraint 'wi' in asm ... From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D53265 llvm-svn: 345810	2018-11-01 02:35:17 +00:00
Zaara Syeda	edefda48d2	[PowerPC] Support operand modifier 'x' in inline asm ... gcc uses operand modifier 'x' in inline asm for VSX registers. Without this modifier, instructions which use VSX numbering for their operands are printed as VMX registers. This patch adds support for the operand modifier 'x'. Differential Revision: https://reviews.llvm.org/D52244 llvm-svn: 342882	2018-09-24 14:01:16 +00:00