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426364 Commits

Author SHA1 Message Date
Benjamin Kramer b3c0918fb4 [AST] Make header self-contained 
There's a dependency in AbstractTypeReader.inc that becomes an error
after D127231.
 2022-06-08 12:36:36 +02:00
LLVM GN Syncbot e21c1b4706 [gn build] Port 916e9052ba 2022-06-08 10:19:18 +00:00
Andrew Ng 3d6fcdf945 [CMake] Improve support for ASAN on Windows with MSVC cl & clang-cl 
Tested with MSVC 2019 (19.29) and LLVM 14.0.4.

Differential Revision: https://reviews.llvm.org/D126706
 2022-06-08 11:16:20 +01:00
Nikolas Klauser 916e9052ba [libc++] Implement ranges::adjacent_find 
Reviewed By: Mordante, var-const, #libc

Spies: libcxx-commits, mgorny

Differential Revision: https://reviews.llvm.org/D126610
 2022-06-08 12:15:03 +02:00
Nikita Popov 10ac235b07 [Docs] Add version support information for opaque pointers (NFC) 
I've seen a few people try to enable opaque pointers with LLVM 14
already. While LLVM 14 has pretty good baseline support, there are
enough missing pieces that you're definitely going to hit assertion
failures if you try this.

Add some wording to make it clear what the support (or planned
support) for opaque/typed pointers is across LLVM 14, 15, and 16.
 2022-06-08 11:54:34 +02:00
Paul Walker d88354213c [SelectionDAG] Remove invalid TypeSize conversion from PromoteIntRes_BITCAST. 
Extend the TypeWidenVector case of PromoteIntRes_BITCAST to work
with TypeSize directly rather than silently casting to unsigned.

To accomplish this I've extended TypeSize with an interface that
essentially allows TypeSize division when both operands have the
same number of dimensions.

There still exists combinations of scalable vector bitcasts that
cause compiler crashes. I call these out by adding "is missing"
entries to sve-bitcast.

Depends on D126957.
Fixes: #55114

Differential Revision: https://reviews.llvm.org/D127126
 2022-06-08 10:30:07 +01:00
Paul Walker a1121c31d8 [SVE] Fix incorrect code generation for bitcasts of unpacked vector types. 
Bitcasting between unpacked scalable vector types of different
element counts is not a NOP because the live elements are laid out
differently.
               01234567
e.g. nxv2i32 = XX??XX??
     nxv4f16 = X?X?X?X?

Differential Revision: https://reviews.llvm.org/D126957
 2022-06-08 10:30:07 +01:00
Nikita Popov 471bfb7016 [Bitcode] Re-enable verify-uselistorder test (NFC) 
This issue has since been fixed, so re-enable the commented RUN
line.
 2022-06-08 11:29:28 +02:00
Max Kazantsev 16c028a8c8 [Test] Add XFAIL test for PR55689 
SCEV issues in dynamically unreached code, see details at https://github.com/llvm/llvm-project/issues/55689

1st reduced test by Nikic!
 2022-06-08 16:01:29 +07:00
Martin Storsjö 20ca739701 [doc] Add release notes about SEH unwind information on ARM 
Differential Revision: https://reviews.llvm.org/D127150
 2022-06-08 11:32:17 +03:00
Matthias Springer 032be23309 [mlir][bufferize] Improve buffer writability analysis 
Find writability conflicts (writes to buffers that are not allowed to be written to) by checking SSA use-def chains. This is better than the current writability analysis, which is too conservative and finds false positives.

Differential Revision: https://reviews.llvm.org/D127256
 2022-06-08 10:11:52 +02:00
Chuanqi Xu 0e10f12844 [NFC] Remove commented cerr debugging loggings 
There are some unused cerr debugging loggings in the codes. It is weird
to remain such commented debug helpers in the product.
 2022-06-08 15:58:06 +08:00
David CARLIER c06ef17359 [Sanitizers] intercept FreeBSD procctl 
Reviewers: vitalybuka, emaster

Reviewed-By: viatelybuka

Differential Revision: https://reviews.llvm.org/D127069
 2022-06-08 08:55:10 +01:00
Benjamin Kramer 6eb0f8e285 [mlir][MemRef] Fix a crash when expanding a scalar shape 
In this case the reassociation is empty, yielding no strides for the
result type.

Differential Revision: https://reviews.llvm.org/D127232
 2022-06-08 09:37:40 +02:00
LLVM GN Syncbot c6d6535a26 [gn build] Port 638b0fb4d6 2022-06-08 07:20:40 +00:00
Nathan James 638b0fb4d6
[ADT][NFC] Early bail out for ComputeEditDistance 
The minimun bound for number of edits is the size difference between the 2 arrays.
If MaxEditDistance is smaller than this, we can bail out early without needing to traverse any of the arrays.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D127070
 2022-06-08 08:20:29 +01:00
lorenzo chelini d48479791f [MLIR][SCF] Improve doc (NFC) 2022-06-08 08:46:36 +02:00
Kito Cheng 7207373e1e Revert "[SplitKit] Handle early clobber + tied to def correctly" 
Revert due to failed on LLVM_ENABLE_EXPENSIVE_CHECKS.

This reverts commit e14d04909d.
 2022-06-08 13:05:35 +08:00
Fangrui Song 311f783960 [CMake] Enable LLVM_ENABLE_PER_TARGET_RUNTIME_DIR by default on Linux 
This makes the LLVM_ENABLE_PROJECTS mode (supported for compiler-rt, deprecated
(D112724) for libcxx/libcxxabi/libunwind) closer to
https://libcxx.llvm.org/BuildingLibcxx.html#bootstrapping-build .
The layout is arguably superior because different libraries of target triples
are in different directories, similar to GCC/Debian multiarch.

When LLVM_DEFAULT_TARGET_TRIPLE is x86_64-unknown-linux-gnu,
`lib/clang/15.0.0/lib/libclang_rt.asan-x86_64.a`
is moved to
`lib/clang/15.0.0/lib/x86_64-unknown-linux-gnu/libclang_rt.asan.a`.

In addition, if the host compiler supports -m32 (multilib),
`lib/clang/15.0.0/lib/libclang_rt.asan-i386.a`
is moved to
`lib/clang/15.0.0/lib/i386-unknown-linux-gnu/libclang_rt.asan.a`.

Reviewed By: mstorsjo, ldionne, #libc

Differential Revision: https://reviews.llvm.org/D107799
 2022-06-07 21:22:38 -07:00
python3kgae 12ca031b0d [DirectX][Fail crash in DXILPrepareModule pass when input has typed ptr. 
Check supportsTypedPointers instead of hasSetOpaquePointersValue when query if has typed ptr.

Reviewed By: beanz

Differential Revision: https://reviews.llvm.org/D127268
 2022-06-07 21:11:24 -07:00
Kito Cheng e14d04909d [SplitKit] Handle early clobber + tied to def correctly 
Spliter will try to extend a live range into `r` slot for a use operand,
that's works on most situaion, however that not work correctly when the operand
has tied to def, and the def operand is early clobber.

Give an example to demo what's wrong:
  0  %0 = ...
 16  early-clobber %0 = Op %0 (tied-def 0), ...
 32  ... = Op %0

Before extend:
 %0 = [0r, 0d) [16e, 32d)

The point we want to extend is 0d to 16e not 16r in this case, but if
we use 16r here we will extend nothing because that already contained
in [16e, 32d).

This patch add check for detect such case and adjust the extend point.

Detailed explanation for testcase: https://reviews.llvm.org/D126047

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D126048
 2022-06-08 11:33:05 +08:00
Kito Cheng cbe22c7943 [RISCV] Testcase to show wrong register allocation result of subreg liveness 
This testcase show the live range isn't construct correctly when subreg
liveness is enabled.

In the testcase `early-clobber-tied-def-subreg-liveness.ll`, first operand of
`vsext.vf2 v8, v16, v0.t` is both def and use, and the use is come from
the memory location of `.L__const._Z3foov.var_49`, it's load and spilled
into stack, and then...v8 is overwrite by another instructions.

```
lui a0, %hi(.L__const._Z3foov.var_49)
addi a0, a0, %lo(.L__const._Z3foov.var_49)
...
vle16.v v8, (a0) # Load value from var_49
...
addi a0, sp, 16
...
vs2r.v v8, (a0) # Spill
...
vl2r.v v8, (a1) # Reload
...
lui a0, %hi(.L__const._Z3foov.var_40)
addi a0, a0, %lo(.L__const._Z3foov.var_40)
vle16.v v8, (a0)     # Load value...into v8???
vmsbc.vx v0, v8, a0  # And use that.
...
vsext.vf2 v8, v16, v0.t # But v8 is here...which is expect value from the reload
```

The `early-clobber-tied-def-subreg-liveness.mir` has more detailed
infomation for that, `%25.sub_vrm2_0` is defined in 64, and used in 464,
and defined again in 464, and we has used an inline asm to clobber all
vector register for trigger spliter.

```
0B      bb.0.entry:
16B       %0:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_49
32B       %1:gpr = ADDI %0:gpr, target-flags(riscv-lo) @__const._Z3foov.var_49
48B       dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
64B       undef %25.sub_vrm2_0:vrn4m2nov0 = PseudoVLE16_V_M2 %1:gpr, 2, 4, implicit $vl, implicit $vtype
80B       %3:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_48
96B       %4:gpr = ADDI %3:gpr, target-flags(riscv-lo) @__const._Z3foov.var_48
112B      %5:vr = PseudoVLE8_V_M1 %4:gpr, 2, 3, implicit $vl, implicit $vtype
128B      %6:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_46
144B      %7:gpr = ADDI %6:gpr, target-flags(riscv-lo) @__const._Z3foov.var_46
160B      %25.sub_vrm2_1:vrn4m2nov0 = PseudoVLE16_V_M2 %7:gpr, 2, 4, implicit $vl, implicit $vtype
176B      %9:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_45
192B      %10:gpr = ADDI %9:gpr, target-flags(riscv-lo) @__const._Z3foov.var_45
208B      %25.sub_vrm2_2:vrn4m2nov0 = PseudoVLE16_V_M2 %10:gpr, 2, 4, implicit $vl, implicit $vtype
224B      INLINEASM &"" [sideeffect] [attdialect], $0:[clobber], ...
240B      %12:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_44
256B      %13:gpr = ADDI %12:gpr, target-flags(riscv-lo) @__const._Z3foov.var_44
272B      dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
288B      %25.sub_vrm2_3:vrn4m2nov0 = PseudoVLE16_V_M2 %13:gpr, 2, 4, implicit $vl, implicit $vtype
304B      $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
320B      %16:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_40
336B      %17:gpr = ADDI %16:gpr, target-flags(riscv-lo) @__const._Z3foov.var_40
352B      %18:vrm2 = PseudoVLE16_V_M2 %17:gpr, 2, 4, implicit $vl, implicit $vtype
368B      $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
384B      %20:gpr = LUI 1048572
400B      %21:gpr = ADDIW %20:gpr, 928
416B      early-clobber %22:vr = PseudoVMSBC_VX_M2 %18:vrm2, %21:gpr, 2, 4, implicit $vl, implicit $vtype
432B      $x0 = PseudoVSETIVLI 2, 9, implicit-def $vl, implicit-def $vtype
448B      $v0 = COPY %22:vr
464B      early-clobber %25.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %25.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, killed $v0, 2, 4, 0, implicit $vl, implicit $vtype
480B      %26:gpr = LUI target-flags(riscv-hi) @var_47
496B      %27:gpr = ADDI %26:gpr, target-flags(riscv-lo) @var_47
512B      PseudoVSSEG4E16_V_M2 %25:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
528B      PseudoRET
```

When spliter will try to split %25:

```
selectOrSplit VRN4M2NoV0:%25 [64r,160r:4)[160r,208r:0)[208r,288r:1)[288r,464e:2)[464e,512r:3) 0@160r 1@208r 2@288r 3@464e 4@64r  L0000000000000030 [160r,512r:0) 0@160r  L00000000000000C0 [208r,512r:0) 0@208r  L0000000000000300 [288r,512r:0) 0@288r  L000000000000000C [64r,464e:1)[464e,512r:0) 0@464e 1@64r  weight:1.179245e-02 w=1.179245e-02
```

```
Best local split range: 64r-208r, 6.999861e-03, 3 instrs
    enterIntvBefore 64r: not live
    leaveIntvAfter 208r: valno 1
    useIntv [64B;216r): [64B;216r):1
  blit [64r,160r:4): [64r;160r)=1(%29)(recalc)
  blit [160r,208r:0): [160r;208r)=1(%29)(recalc)
  blit [208r,288r:1): [208r;216r)=1(%29)(recalc) [216r;288r)=0(%28)(recalc)
  blit [288r,464e:2): [288r;464e)=0(%28)(recalc)
  blit [464e,512r:3): [464e;512r)=0(%28)(recalc)
  rewr %bb.0    464e:0  early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %25.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
  rewr %bb.0    288r:0  %28.sub_vrm2_3:vrn4m2nov0 = PseudoVLE16_V_M2 %13:gpr, 2, 4, implicit $vl, implicit $vtype
  rewr %bb.0    208r:1  %29.sub_vrm2_2:vrn4m2nov0 = PseudoVLE16_V_M2 %10:gpr, 2, 4, implicit $vl, implicit $vtype
  rewr %bb.0    160r:1  %29.sub_vrm2_1:vrn4m2nov0 = PseudoVLE16_V_M2 %7:gpr, 2, 4, implicit $vl, implicit $vtype
  rewr %bb.0    64r:1   undef %29.sub_vrm2_0:vrn4m2nov0 = PseudoVLE16_V_M2 %1:gpr, 2, 4, implicit $vl, implicit $vtype
  rewr %bb.0    464B:0  early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %28.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
  rewr %bb.0    512B:0  PseudoVSSEG4E16_V_M2 %28:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
  rewr %bb.0    216B:1  undef %28.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %29.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0@216r 1@288r 2@464e  L000000000000000C [216r,216d:0)[464e,512r:1) 0@216r 1@464e  L0000000000000300 [288r,512r:0) 0@288r  L00000000000000C0 [216r,512r:0) 0@216r  L0000000000000030 [216r,512r:0) 0@216r  weight:8.706897e-03
Enqueuing %28
queuing new interval: %29 [64r,160r:0)[160r,208r:1)[208r,216r:2) 0@64r 1@160r 2@208r  L000000000000000C [64r,216r:0) 0@64r  L00000000000000C0 [208r,216r:0) 0@208r  L0000000000000030 [160r,216r:0) 0@160r  weight:1.097826e-02
Enqueuing %29
```

The live range of first part subreg of %25 is become [216r,216d:0)[464e,512r:1),
however first live range should live until 464e rather than just live
and [216r,216d:0).

And then the register allocator allocated wrong result accroding the
live range info.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D126047
 2022-06-08 11:27:24 +08:00
Nathan Lanza f46ce03734 [MLIR] Add an install target for mlir-libraries 
This is required for the distribution system for installing the
mlir-libraries component. This is copied from clang's equivalent
feature.

Differential Revision: https://reviews.llvm.org/D126837
 2022-06-07 22:57:07 -04:00
Chuanqi Xu 733d7cf964 [Debug] [Coroutines] Add deref operator for non complex expression 
Background:

When we construct coroutine frame, we would insert a dbg.declare
intrinsic for it:
```
%hdl = call void @llvm.coro.begin() ; would return coroutine handle
call void @llvm.dbg.declare(metadata ptr %hdl, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
```

And in the splitted coroutine, it looks like:
```
define void @coro_func.resume(ptr *hdl) {
entry.resume:
    call void @llvm.dbg.declare(metadata ptr %hdl, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
}
```

And we would salvage the debug info by inserting a new alloca here:
```
define void @coro_func.resume(ptr %hdl) {
entry.resume:
    %frame.debug = alloca ptr
    call void @llvm.dbg.declare(metadata ptr %frame.debug, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
    store ptr %hdl, %frame.debug
}
```

But now, the problem comes since the `dbg.declare` refers to the address
of that alloca instead of actual coroutine handle. I saw there are codes
to solve the problem but it only applies to complex expression only. I
feel if it is OK to relax the condition to make it work for
`__coro_frame`.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D126277
 2022-06-08 10:53:51 +08:00
Nathan Lanza 9b3c5cba9f Update the ProgrammersManual explanation for ilist and iplist 
They are now `using` aliases and thus the comments about iplist are now
incorrect. Remove them here.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D95210
 2022-06-07 22:50:04 -04:00
Sunho Kim 2094fad009 [JITLink][ELF][AArch64] Implement ADR_GOT_PAGE, LD64_GOT_LO12_NC. 
This patch implements two most commonly used Global Offset Table relocations in
ELF/AARCH64: R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC. It
implements the GOT table manager by extending the existing
PerGraphGOTAndPLTStubsBuilder. A future patch will unify this with the MachO
implementation to produce a generic aarch64 got table manager.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D127057
 2022-06-07 18:20:37 -07:00
Leonard Chan b37d84aa8d Reland "[NFC][compiler-rt][asan] Unify asan and lsan allocator settings" 
I believe this should've been fixed with 4b15e665f8
which landed after this initial patch, but I reverted too early before I
saw the builder turn green again.
 2022-06-07 18:09:48 -07:00
Joe Loser b2aec7e6ed
Revert "[libc++][test] Mark ranges.transform.pass.cpp UNSUPPORTED for AIX" 
This reverts commit 3583826bb5.

Instead of marking the test unsupported for AIX, the choice is to bump the
timeout for CI as done in 76c7e1f2a8 and
222bd83d50

Differential Revision: https://reviews.llvm.org/D127242
 2022-06-07 19:00:56 -06:00
Wael Yehia 0952cf5bbb [InstCombine] decomposeSimpleLinearExpr should bail out on negative operands. 
InstCombine tries to rewrite

  %prod = mul nsw i64 %X,   Scale
  %acc = add nsw i64 %prod,   Offset
  %0 = alloca i8, i64 %acc, align 4
  %1 = bitcast i8* %0 to i32*
  Use ( %1 )

into

  %prod = mul nsw i64 %X,   Scale/4
  %acc = add nsw i64 %prod,   Offset/4
  %0 = alloca i32, i64 %acc, align 4
  Use (%0)

But it assumes Scale is unsigned, and performs an unsigned division.
So we should bail out if Scale cannot be interpreted as an unsigned safely.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D126546
 2022-06-08 00:57:25 +00:00
Lang Hames 1deaa9b8bd [JITLink][ELF][AArch64] Implement R_AARCH64_ABS64 relocation type. 
Implement R_AARCH64_ABS64 relocation entry. This relocation type is generated
when creating a static function pointer to symbol.

Reviewed By: lhames, sgraenitz

Differential Revision: https://reviews.llvm.org/D126658
 2022-06-07 17:56:10 -07:00
Kevin Athey 67069e1980 [MSAN] exclude android from pthread_getaffinity_np interceptor 
Depends on https://reviews.llvm.org/D127185.

Differential Revision: https://reviews.llvm.org/D127264
 2022-06-07 17:53:32 -07:00
Leonard Chan 13eb4fc3ce Revert "[NFC][compiler-rt][asan] Unify asan and lsan allocator settings" 
This reverts commit dd045ddffc.

This broke the sanitizer-windows builder at https://lab.llvm.org/buildbot/#/builders/127/builds/30751.
 2022-06-07 17:34:29 -07:00
Sunho Kim ab472c9615 [JITLink][ELF][AArch64] Implement R_AARCH64_LDST*_ABS_LO12_NC relocation types. 
Implement R_AARCH64_LDST*_ABS_LO12_NC relocaiton entries by reusing PageOffset21
generic relocation edge. The difference between MachO backend is that in ELF,
the shift value is explicitly given by relocation type. lld generates the
relocation type that matches with instruction bitwidth, so getting the shift
value implicitly from instruction bytes should be fine in typical use cases.
 2022-06-07 17:32:09 -07:00
Leonard Chan d1fb0a5a63 Fix for e1d84c421d 
One of the checks in realloc_too_big.c actually printed a regular warning
and not an OOM error, so the check shouldn't be updated.
 2022-06-07 17:28:24 -07:00
Leonard Chan 4b15e665f8 [compiler-rt][lsan] Choose lsan allocator via SANITIZER_CAN_USE_ALLOCATOR64 
Rather than checking a bunch of individual platforms.

Differential Revision: https://reviews.llvm.org/D126825
 2022-06-07 17:23:38 -07:00
Leonard Chan dd045ddffc [NFC][compiler-rt][asan] Unify asan and lsan allocator settings 
This updates existing asan allocator settings to use the same allocator settings as what lsan uses for platforms where they already match.

Differential Revision: https://reviews.llvm.org/D126927
 2022-06-07 17:21:19 -07:00
Derek Schuff 1e29c3a12f [WebAssembly][Objcopy] Check that --only-keep-debug removes known sections 
NFC; Just update the test to ensure that both known and custom sections
are removed.
Review left over from https://reviews.llvm.org/D126509
 2022-06-07 16:47:50 -07:00
Leonard Chan e1d84c421d [compiler-rt][sanitizer] Have all OOM-related error messages start with the same format 
This way downstream tools that read sanitizer output can differentiate between OOM errors
reported by sanitizers from other sanitizer errors.

Changes:

- Introduce ErrorIsOOM for checking if a platform-specific error code from an "mmap" is an OOM err.
- Add ReportOOMError which just prepends this error message to the start of a Report call.
- Replace some Reports for OOMs with calls to ReportOOMError.
- Update necessary tests.

Differential Revision: https://reviews.llvm.org/D127161
 2022-06-07 16:46:01 -07:00
Lang Hames 5368c685d9 [ORC-RT] Remove a stale comment. 2022-06-07 16:42:37 -07:00
Sunho Kim 25a9fb12e0 [JITLink][ELF][AArch64] Implement ADR_PREL_PG_HI21, ADD_ABS_LO12_NC. 
Implements R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADD_ABS_LO12_NC fixup edges
using the generic aarch64 patch edges.

Reviewed By: lhames, sgraenitz

Differential Revision: https://reviews.llvm.org/D126287
 2022-06-07 16:42:37 -07:00
Kevin Athey 828c94c0f6 [MSAN] Add interceptor for pthread_getaffinity_np. 
Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D127185
 2022-06-07 16:27:44 -07:00
Kevin Athey 69cd7417f0 Add checks for -lresolv to sanitizer-ld test. 
These were missed in https://reviews.llvm.org/D127145.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D127177
 2022-06-07 16:07:02 -07:00
Wolfgang Pieb 213eb424e8 Revert "[Metadata] Add a resize capability to MDNodes and add a push_back interface to MDNodes" 
This reverts commit e3f6eda8c6.

Failure in unittest on https://lab.llvm.org/buildbot*builders/171/builds/15666
 2022-06-07 15:48:31 -07:00
Sanjay Patel cae993d4c8 [InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits 
If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X

https://alive2.llvm.org/ce/z/_UzTMP

This is the reverse-order shift sibling to 82040d414b ( D127122 ).
It seems likely that we would want to add this to the SDAG version of
the code too to keep it on par with IR.
 2022-06-07 18:43:27 -04:00
Sanjay Patel 0856a6cb7a [InstCombine] add tests for left-shift-of-right-shifted constant; NFC 
The tests are adapted from the sibling folds' tests (see D127122).
 2022-06-07 18:43:27 -04:00
Sanjay Patel a4d2c5ecaa [InstCombine] reduce code duplication for accessing type; NFC 2022-06-07 18:43:27 -04:00
owenca b5b33fbffb [clang-format] Skip parsing a block if it's nested too deep 
Fixes #55912.

Differential Revision: https://reviews.llvm.org/D127183
 2022-06-07 15:28:03 -07:00
Pengxuan Zheng 1b2c8b945b [NFC][test] Improve ecsymbols.test 
* The yaml input is inlined into the test file.
* Unnecessary members and fields are removed.

Reviewed By: thieta

Differential Revision: https://reviews.llvm.org/D127235
 2022-06-07 15:26:05 -07:00
Nico Weber 28c078e2c7 [gn build] (manually) port f3966eaf86 (_LIBCPP_ENABLE_DEBUG_MODE) 2022-06-07 18:13:13 -04:00
Douglas Yung 7805ae257f Revert "[clang-diff] Fix assertion error when dealing with wide strings" 
This reverts commit e80748ff88.

This was causing a test failure on a buildbot: https://lab.llvm.org/buildbot/#/builders/139/builds/22964
 2022-06-07 14:58:10 -07:00