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19726 Commits

Author SHA1 Message Date
Jim Grosbach 42ba6286b6 ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

llvm-svn: 144315
 2011-11-10 20:48:53 +00:00
Jim Grosbach c14871cc67 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach 61db5a59f7 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Daniel Dunbar b538095011 build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for 
consistency with other targets.

llvm-svn: 144292
 2011-11-10 15:35:14 +00:00
Nadav Rotem 0a2f797dec AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266
 2011-11-10 06:54:20 +00:00
Chad Rosier 3fbd094ad9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Daniel Dunbar 807c6e4e5f build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255
 2011-11-10 01:16:48 +00:00
Daniel Dunbar 233c9304a8 llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253
 2011-11-10 00:50:07 +00:00
Daniel Dunbar 1c04e14447 llvm-build: Change CBackend and CppBackend to not use library_name. This will 
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

llvm-svn: 144251
 2011-11-10 00:49:55 +00:00
Daniel Dunbar 82219ad4dc llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250
 2011-11-10 00:49:51 +00:00
Jim Grosbach a48485a37f Tidy up. 
llvm-svn: 144244
 2011-11-10 00:02:33 +00:00
Jim Grosbach 25bc090170 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Eli Friedman 2d4055b683 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
llvm-svn: 144241
 2011-11-09 23:36:02 +00:00
Chad Rosier 2f27fab6ed The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Nadav Rotem 1938482bfa AVX2: Add patterns for variable shift operations 
llvm-svn: 144212
 2011-11-09 21:22:13 +00:00
Devang Patel 2f70bcdb94 Remove unnecessary include. 
llvm-svn: 144211
 2011-11-09 21:11:02 +00:00
Nadav Rotem 79135d844d Add AVX2 support for vselect of v32i8 
llvm-svn: 144187
 2011-11-09 13:21:28 +00:00
Craig Topper f87a2bef51 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. 
llvm-svn: 144179
 2011-11-09 09:37:21 +00:00
Craig Topper c9eb09d3b8 Add instruction selection for AVX2 integer comparisons. 
llvm-svn: 144176
 2011-11-09 08:06:13 +00:00
Craig Topper 8c8a431057 Add AVX2 instruction lowering for add, sub, and mul. 
llvm-svn: 144174
 2011-11-09 07:28:55 +00:00
Chad Rosier 595d419427 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Evan Cheng 94307f6ba6 Hide cpu name checking in ARMSubtarget. 
llvm-svn: 144154
 2011-11-09 01:57:03 +00:00
Bruno Cardoso Lopes d5edb3847a Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

llvm-svn: 144139
 2011-11-08 22:26:47 +00:00
Evan Cheng c3770ac687 Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
llvm-svn: 144123
 2011-11-08 21:21:09 +00:00
Chad Rosier 0439cfc41f ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

llvm-svn: 144122
 2011-11-08 21:12:00 +00:00
Lang Hames b85fcd07df Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.

llvm-svn: 144102
 2011-11-08 18:56:23 +00:00
Pete Cooper 82cd9e81fc Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
 2011-11-08 18:42:53 +00:00
Bruno Cardoso Lopes 71133fe9c6 This patch handles unaligned loads and stores in Mips JIT. Mips backend 
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

llvm-svn: 144081
 2011-11-08 12:47:11 +00:00
NAKAMURA Takumi 05aa1a42c3 PPCInstrInfo.cpp: Fix one "unused" warning. 
llvm-svn: 144071
 2011-11-08 04:00:07 +00:00
Eli Friedman 6f84fed675 Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
llvm-svn: 144057
 2011-11-08 01:43:53 +00:00
Evan Cheng 91b56e0390 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
llvm-svn: 144052
 2011-11-08 00:31:58 +00:00
Chad Rosier 5de1bea5c9 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier fa75530ff0 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. 
llvm-svn: 144021
 2011-11-07 21:43:40 +00:00
Akira Hatanaka 2216f73676 Various Mips64 floating point instruction patterns. 
llvm-svn: 144019
 2011-11-07 21:38:58 +00:00
Akira Hatanaka b2d37760a2 Add definition of the base class for floating point comparison instructions 
and add Mips64's version too.

llvm-svn: 144018
 2011-11-07 21:37:33 +00:00
Akira Hatanaka 81c14002dc Add code needed for copying between 64-bit integer and floating pointer 
registers.

llvm-svn: 144017
 2011-11-07 21:35:45 +00:00
Akira Hatanaka 1537e297e1 Add definitions of 64-bit instructions which move data between integer and 
floating pointer registers.

llvm-svn: 144016
 2011-11-07 21:32:58 +00:00
Benjamin Kramer 69d57cf9c4 Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Benjamin Kramer 03d73e47b4 Simplify code. No functionality change. 
llvm-svn: 144012
 2011-11-07 21:00:43 +00:00
Jakob Stoklund Olesen 0241308954 Expand V_SET0 to xorps by default. 
The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

llvm-svn: 143996
 2011-11-07 19:15:58 +00:00
Akira Hatanaka 2b8d1f163f Add definition of 64-bit load upper immediate. 
llvm-svn: 143994
 2011-11-07 19:10:49 +00:00
Akira Hatanaka 2f4480046b Include RegSaveAreaSize in the computation of stack size. 
llvm-svn: 143993
 2011-11-07 19:07:35 +00:00
Akira Hatanaka 7bcecd486f Define functions that get or set the size of area on callee's stack frame which 
is used to save va_arg or byval arguments passed in registers.

llvm-svn: 143992
 2011-11-07 19:06:10 +00:00
Akira Hatanaka d9c2e46cfb Use array_lengthof to compute the number of iterations of a loop. 
llvm-svn: 143991
 2011-11-07 19:03:40 +00:00
Akira Hatanaka cf7e5b0976 Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 
when shift amount is larger than 32.

llvm-svn: 143990
 2011-11-07 19:01:49 +00:00
Akira Hatanaka 770f0646db Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.

llvm-svn: 143989
 2011-11-07 18:59:49 +00:00
Akira Hatanaka d5c1329078 Add 64-bit to 32-bit trunc pattern. 
llvm-svn: 143988
 2011-11-07 18:57:41 +00:00
Craig Topper a6d409d543 Add AVX2 variable shift instructions and intrinsics. 
llvm-svn: 143915
 2011-11-07 08:26:24 +00:00
Craig Topper ff39be0afc Add AVX2 VPMOVMASK instructions and intrinsics. 
llvm-svn: 143904
 2011-11-07 03:20:35 +00:00
Craig Topper e122dcbf4a Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
llvm-svn: 143902
 2011-11-07 02:00:04 +00:00