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11 Commits

Author SHA1 Message Date
Craig Topper ef1807fb73 [AVX-512] Add more varied alignments to tests for storing the lower 128-bits of a 256 or 512-bit subvector extract. 
llvm-svn: 286343
 2016-11-09 05:38:47 +00:00
Craig Topper 28e3dfc02b [AVX-512] Use alignedstore256 in patterns that look for stores of the lower 256-bits of a 512-bit vector to use a 256-bit aligned store. 
Previously we were only checking for 16 byte alignment instead of 32 byte alignment. Fixes PR30947.

llvm-svn: 286342
 2016-11-09 05:31:57 +00:00
Craig Topper abf5041537 [AVX-512] Add test cases to demonstrate PR30947. We accidentally use 32 byte aligned store instructions when the original store was only 16 byte aligned if the store is from the lower bits of a subvector extract. 
llvm-svn: 286341
 2016-11-09 05:31:53 +00:00
Craig Topper d4e580705d [AVX-512] Add missing patterns for selecting masked vector extracts that started from shuffles. 
llvm-svn: 285546
 2016-10-31 05:55:57 +00:00
Craig Topper c48c029610 [AVX-512] Fix duplicate column in AVX512 execution dependency table that was preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types. 
llvm-svn: 277327
 2016-08-01 07:55:33 +00:00
Craig Topper 4c53e60360 [AVX512] Add VLX packed move instructions to the execution dependency fix pass and update tests. 
llvm-svn: 277304
 2016-07-31 20:20:01 +00:00
Matthias Braun 152e7c8b12 VirtRegMap: Replace some identity copies with KILL instructions. 
An identity COPY like this:
   %AL = COPY %AL, %EAX<imp-def>
has no semantic effect, but encodes liveness information: Further users
of %EAX only depend on this instruction even though it does not define
the full register.

Replace the COPY with a KILL instruction in those cases to maintain this
liveness information. (This reverts a small part of r238588 but this
time adds a comment explaining why a KILL instruction is useful).

llvm-svn: 274952
 2016-07-09 00:19:07 +00:00
Craig Topper 95bdabd338 [AVX512] Add patterns to implement stores of extracts of least signficant subvectors using XMM or YMM stores instead of the vector extract instructions. 
Similar is already done for AVX and we had lost it going to AVX512VL.

llvm-svn: 270383
 2016-05-22 23:44:33 +00:00
Craig Topper db960eddfa [AVX512] Add patterns for extracting subvectors and storing to memory. 
llvm-svn: 270334
 2016-05-21 22:50:14 +00:00
James Y Knight 7c905063c5 Make utils/update_llc_test_checks.py note that the assertions are 
autogenerated.

Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.

llvm-svn: 253917
 2015-11-23 21:33:58 +00:00
Igor Breger defab3c1ef AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation. 
This instructions doesn't have intrincis.
Added tests for lowering and encoding.

Differential Revision: http://reviews.llvm.org/D12317

llvm-svn: 249688
 2015-10-08 12:55:01 +00:00