be1f314a47
Remove the X86 and PowerPC Simple instruction selectors; their time has
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passed.
llvm-svn: 22886
2005-08-18 23:53:15 +00:00
c6aa80668e
add a beta option for turning on dag->dag isel
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llvm-svn: 22837
2005-08-17 19:33:30 +00:00
73785d2ef2
Turn loop strength reduction on by default.
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Only run createLowerConstantExpressionsPass for the simple isel. The DAG
isel has no need for it.
llvm-svn: 22794
2005-08-15 23:47:04 +00:00
a22bf778c9
Remove support for 64b PPC, it's been broken for a long time. It'll be
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back once a DAG->DAG ISel exists.
llvm-svn: 22778
2005-08-13 05:59:16 +00:00
983a415b6a
Consolidate the GPOpt stuff to all use the Subtarget, instead of still
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depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
llvm-svn: 22688
2005-08-05 22:05:03 +00:00
8c636bf8b2
don't crash when running the PPC backend on non-ppc hosts without specifying
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a subtarget.
llvm-svn: 22677
2005-08-05 16:17:22 +00:00
295ea90634
Use the new subtarget support to automatically choose the correct ABI
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and asm printer for PowerPC if one is not specified.
llvm-svn: 22659
2005-08-04 20:49:48 +00:00
3bcfcd9474
Add Subtarget support to PowerPC. Next up, using it.
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llvm-svn: 22644
2005-08-04 07:12:09 +00:00
5f4ef3c5a8
Eliminate all remaining tabs and trailing spaces.
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llvm-svn: 22523
2005-07-27 06:12:32 +00:00
a9443f29b0
Support building non-PIC
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Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.
llvm-svn: 22494
2005-07-21 20:44:43 +00:00
53208ecf34
revert to using 4-byte alignment for doubles, as specified by the ABI
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llvm-svn: 22493
2005-07-21 19:17:18 +00:00
8465fe8b4b
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
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8-byte align doubles.
llvm-svn: 22486
2005-07-20 22:42:00 +00:00
0851f1aaa1
Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being
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automatically generated from a target description.
llvm-svn: 22470
2005-07-19 16:51:05 +00:00
f11f48ba61
Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile
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interface.
llvm-svn: 22282
2005-06-25 02:48:37 +00:00
b440243e94
Remove trailing whitespace
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llvm-svn: 21425
2005-04-21 23:30:14 +00:00
779c5cbb44
Make pattern isel default for ppc
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Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
llvm-svn: 21309
2005-04-15 22:12:16 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
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Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
7ec19b4d5a
Implement more of the PPC32 Pattern ISel:
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1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel
Remove dead arguments from getGlobalBaseReg in the simple ISel
llvm-svn: 20810
2005-03-24 06:28:42 +00:00
20e7e28ee7
Addition of the PPC32 Pattern ISel. While it is far from complete, it will
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be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.
llvm-svn: 20805
2005-03-24 04:41:43 +00:00
5b5caaf3cd
cleanup the cfg after lsr
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llvm-svn: 20410
2005-03-02 21:56:00 +00:00
c8bb99760a
Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on
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Loop Strength Reduction.
llvm-svn: 20399
2005-03-02 06:19:22 +00:00
17550c456c
Use the target triple to pick this target.
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llvm-svn: 18830
2004-12-12 17:40:28 +00:00
c0f8a1c721
The LLVM bool type shall have 1 byte alignment on PPC.
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llvm-svn: 18311
2004-11-28 21:16:45 +00:00
497a622376
The JIT works enough
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llvm-svn: 18228
2004-11-25 04:14:54 +00:00
24ad93f55c
Remove this method.
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llvm-svn: 18159
2004-11-23 18:47:42 +00:00
7e7a08dba5
Don't return value from void function. This is only temporary anyway while
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the JIT is made to work!
llvm-svn: 18155
2004-11-23 10:04:49 +00:00
5369ab3e24
Be really paranoid about not breaking stuff yet
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llvm-svn: 18152
2004-11-23 06:56:18 +00:00
f5363dc789
Move JITInfo from PPCTM to PPC32TM
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llvm-svn: 18140
2004-11-23 05:56:40 +00:00
6f01b4cf1f
Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode
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llvm-svn: 18038
2004-11-20 04:17:17 +00:00
ff43ef3cc5
Disable the JIT until it can sorta kinda work.
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llvm-svn: 17230
2004-10-25 20:53:41 +00:00
3acdb7fa1b
bling bling!
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llvm-svn: 16873
2004-10-10 16:26:13 +00:00
4bfceb1ed5
All PPC instructions are now auto-printed
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32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
llvm-svn: 16163
2004-09-04 05:00:00 +00:00
7c16caa336
Changes For Bug 352
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Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
f1cd650251
Do not register ppc64 yet, as it breaks the SparcV9 backend
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llvm-svn: 15955
2004-08-20 18:09:18 +00:00
f73c87b36c
LR needs to be saved at 16-byte offset on a 64-bit arch
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llvm-svn: 15929
2004-08-19 21:36:14 +00:00
ba7fe16dbf
No need for an `is64bit' flag
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llvm-svn: 15857
2004-08-17 05:06:47 +00:00
412602d7d9
Replace PowerPCPEI.cpp with target independant PrologEpilogInserter
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llvm-svn: 15746
2004-08-14 22:16:36 +00:00
af77fe4097
Disable PPC64 backend by default because LLC cannot choose automatically between
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SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.
llvm-svn: 15688
2004-08-12 17:16:43 +00:00
c94c0f75f4
* Move AIX into the llvm namespace to be accessed from RegisterInfo
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* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer
llvm-svn: 15672
2004-08-11 23:47:08 +00:00
7224ee1e4c
Hyphenate ##-bit and remove first-person from comments.
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llvm-svn: 15663
2004-08-11 13:35:44 +00:00
f17ea0f7b7
Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer.
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llvm-svn: 15662
2004-08-11 07:40:04 +00:00
e67a212267
Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest.
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llvm-svn: 15636
2004-08-11 00:11:25 +00:00
eca36a5aa0
CodePrinter -> AsmPrinter
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llvm-svn: 15599
2004-08-09 22:27:45 +00:00
a8dcf2423e
Changes commited for Nate Begeman:
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Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
llvm-svn: 15536
2004-08-06 06:58:50 +00:00
09396bf158
Run the branch selection pass right before the asm printer.
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Patch by Nate Begeman.
llvm-svn: 15285
2004-07-27 18:39:34 +00:00
4fb48609dc
Bool alignment on MacOSX/PowerPC is 4 bytes.
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llvm-svn: 15122
2004-07-23 01:11:46 +00:00
75f3291ef3
Shorts are aligned to 2 bytes, bools to 1 byte (in structs).
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llvm-svn: 15048
2004-07-20 20:59:57 +00:00
dff882a230
Double alignment in structs is 4 bytes, not 8. Patch by Nate Begeman.
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llvm-svn: 15034
2004-07-20 15:43:25 +00:00
e6f4a5ebb0
We don't really need to #include IPO.h into this file.
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llvm-svn: 14911
2004-07-17 18:37:46 +00:00
a6b9a566b9
Define double alignment as 8 bytes now that assert(DoubleAlignment == PointerSize)
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has been eliminated
llvm-svn: 14891
2004-07-16 19:32:12 +00:00
Nate Begeman