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680 Commits

Author SHA1 Message Date
Nate Begeman 93c4bc6dca ISD::OR, and it's accompanying SelectBitfieldInsert 
llvm-svn: 22889
 2005-08-19 00:38:14 +00:00
Nate Begeman be1f314a47 Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.

llvm-svn: 22886
 2005-08-18 23:53:15 +00:00
Nate Begeman 33acb2c135 Add shifts. 
llvm-svn: 22884
 2005-08-18 23:38:00 +00:00
Chris Lattner 4bd805e785 Fix operand numbers by marking variable arity nodes as such and by fixing 
the operand lists of a few other nodes.

llvm-svn: 22883
 2005-08-18 23:25:33 +00:00
Chris Lattner 51e851d0e6 MFLR doesn't take an operand, the LR register is implicit 
llvm-svn: 22882
 2005-08-18 23:24:50 +00:00
Chris Lattner 4e00ff6e70 Move this to the emitter 
llvm-svn: 22877
 2005-08-18 20:08:53 +00:00
Jim Laskey 18b9b8df86 More optimal solution for loading constants. 
llvm-svn: 22870
 2005-08-18 18:58:23 +00:00
Chris Lattner 015d73996d After selecting the instructions for a basic block, emit the instructions 
llvm-svn: 22869
 2005-08-18 18:46:06 +00:00
Chris Lattner 15b5c7ca84 remove some unused stuff 
llvm-svn: 22866
 2005-08-18 18:34:00 +00:00
Nate Begeman d16a26a8d4 Fix int foo() { return 65535; } by using the top 16 bits of the constant 
as the argument to LIS rather than the result of HA16(constant).

The DAG->DAG ISel was already doing the right thing.

llvm-svn: 22865
 2005-08-18 18:14:49 +00:00
Nate Begeman d32638706a Improve ISD::Constant codegen. 
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr

llvm-svn: 22864
 2005-08-18 18:01:39 +00:00
Chris Lattner 37faf35b35 replace switch stmt with an assert, generate li 0 instead of lis 0 for 0, 
to make the code follow people's expectations better.

llvm-svn: 22861
 2005-08-18 17:16:52 +00:00
Jim Laskey 32d4c85278 Handle loading of 0x????0000 constants with a single instruction. 
llvm-svn: 22858
 2005-08-18 15:52:30 +00:00
Nate Begeman b3821a3943 Add support for ISD::AND, and its various optimized forms. 
llvm-svn: 22857
 2005-08-18 07:30:46 +00:00
Nate Begeman cfb9a74c2e Maintain consistency in negating things 
llvm-svn: 22855
 2005-08-18 05:44:50 +00:00
Nate Begeman 72d6f8800d Implement XOR, remove a broken sign_extend_inreg case 
llvm-svn: 22854
 2005-08-18 05:00:13 +00:00
Nate Begeman 4bfb4a215d Add a bunch more simple nodes. 
llvm-svn: 22851
 2005-08-18 03:04:18 +00:00
Nate Begeman 457367f14c Add a couple more nodes that are easy to handle 
llvm-svn: 22850
 2005-08-18 00:53:47 +00:00
Nate Begeman 74d5529b88 Be fruitful and multiply! 
llvm-svn: 22849
 2005-08-18 00:21:41 +00:00
Jim Laskey 04160c6d8d Better version of isIntImmediate. 
llvm-svn: 22848
 2005-08-18 00:15:15 +00:00
Nate Begeman 3fcf47d8f0 Teach the DAG->DAG ISel about FNEG, and how it can be used to invert 
several of the PowerPC opcodes that come in both negated and non-negated
forms.

llvm-svn: 22845
 2005-08-17 23:46:35 +00:00
Chris Lattner c6aa80668e add a beta option for turning on dag->dag isel 
llvm-svn: 22837
 2005-08-17 19:33:30 +00:00
Chris Lattner 43ff01e2e6 initial hack at a dag->dag instruction selector. This is obviously woefully 
incomplete, but it is a start.  It handles basic argument/retval stuff, immediates,
add and sub.

llvm-svn: 22836
 2005-08-17 19:33:03 +00:00
Chris Lattner f61cce952b add prototype, remove dead proto 
llvm-svn: 22835
 2005-08-17 19:32:03 +00:00
Chris Lattner 63f774ec6e Fix a few small typos I noticed when converting this over to the DAG->DAG 
selector.  Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.

llvm-svn: 22819
 2005-08-17 01:25:14 +00:00
Jim Laskey 9828f26cf1 Removed UINT_TO_FP and SINT_TO_FP from ISel outright. 
llvm-svn: 22818
 2005-08-17 01:14:38 +00:00
Jim Laskey 5909c8b10a Remove ISel code generation for UINT_TO_FP and SINT_TO_FP. Now asserts if 
marked as legal.

llvm-svn: 22816
 2005-08-17 00:41:40 +00:00
Jim Laskey 6267b2c97c Make UINT_TO_FP and SINT_TO_FP use generic expansion. 
llvm-svn: 22815
 2005-08-17 00:40:22 +00:00
Nate Begeman 784c8068a7 Implement a couple improvements: 
Remove dead code in ISD::Constant handling
Add support for add long, imm16

We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr

instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr

llvm-svn: 22811
 2005-08-17 00:20:08 +00:00
Chris Lattner 79f5ebc7b9 updates for changes in nodes 
llvm-svn: 22808
 2005-08-16 21:58:15 +00:00
Nate Begeman 371e49515d Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty 
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.

llvm-svn: 22805
 2005-08-16 19:49:35 +00:00
Chris Lattner f22556d3ad Pull the LLVM -> DAG lowering code out of the pattern selector so that it 
can be shared with the DAG->DAG selector.

llvm-svn: 22799
 2005-08-16 17:14:42 +00:00
Chris Lattner 73785d2ef2 Turn loop strength reduction on by default. 
Only run createLowerConstantExpressionsPass for the simple isel.  The DAG
isel has no need for it.

llvm-svn: 22794
 2005-08-15 23:47:04 +00:00
Jim Laskey 24b84072ea Broke 80 column rule. 
llvm-svn: 22792
 2005-08-15 17:35:26 +00:00
Jim Laskey 42623a9539 Changed code gen for int to f32 to use rounding. This makes FP results 
consistent with gcc.

llvm-svn: 22791
 2005-08-15 17:14:19 +00:00
Nate Begeman d5e739dcc2 Fix last night's PPC32 regressions by 
1. Not selecting the false value of a select_cc in the false arm, which
   isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
   Expander.

llvm-svn: 22789
 2005-08-14 18:38:32 +00:00
Nate Begeman 83f6b98c42 Make FP_TO_UINT Illegal. This allows us to generate significantly better 
codegen for FP_TO_UINT by using the legalizer's SELECT variant.

Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node.  This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
        li r2, 5
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        li r2, 9
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr

insted of:
_foo:
        li r2, 5
        li r5, 9
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        or r2, r5, r5
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr

llvm-svn: 22784
 2005-08-14 01:17:16 +00:00
Nate Begeman a22bf778c9 Remove support for 64b PPC, it's been broken for a long time. It'll be 
back once a DAG->DAG ISel exists.

llvm-svn: 22778
 2005-08-13 05:59:16 +00:00
Jim Laskey 35960708b7 Fix for 2005-08-12-rlwimi-crash.ll. Make allowance for masks being shifted to 
zero.

llvm-svn: 22773
 2005-08-12 23:52:46 +00:00
Jim Laskey a568700618 1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and 
(~x)|y and x|(~y) yielding ORC.

llvm-svn: 22771
 2005-08-12 23:38:02 +00:00
Jim Laskey a50f770a2c 1. Added the function isOpcWithIntImmediate to simplify testing of operand with 
specified opcode and an integer constant right operand.

2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied after a mask.

llvm-svn: 22761
 2005-08-11 21:59:23 +00:00
Chris Lattner d418d752f4 Tidied up the use of dyn_cast<ConstantSDNode> by using isIntImmediate more. 
Patch by Jim Laskey.

llvm-svn: 22760
 2005-08-11 17:56:50 +00:00
Chris Lattner c5e1312baa Use a more efficient method of creating integer and float virtual registers 
(avoids an extra level of indirection in MakeReg).

  defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
  defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)

  s/MakeReg(MVT::i32)/MakeIntReg/
  s/MakeReg(MVT::f64)/MakeFPReg/

Patch by Jim Laskey!

llvm-svn: 22759
 2005-08-11 17:15:31 +00:00
Nate Begeman 5646b181e8 Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely 
reflects what the hardware is capable of.  This significantly simplifies
the CC handling logic throughout the ISel.

llvm-svn: 22756
 2005-08-10 20:52:09 +00:00
Chris Lattner 3428b95634 Changes for PPC32ISelPattern.cpp 
1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.

Patch by Jim Laskey

llvm-svn: 22754
 2005-08-10 18:11:33 +00:00
Chris Lattner aeedcc7fc2 Changed the XOR case to use the isOprNot predicate. 
Patch by Jim Laskey!

llvm-svn: 22750
 2005-08-10 16:35:46 +00:00
Chris Lattner 67d0753773 1. Refactored handling of integer immediate values for add, or, xor and sub. 
New routine: ISel::SelectIntImmediateExpr
  2. Now checking use counts of large constants.  If use count is > 2 then drop
  thru so that the constant gets loaded into a register.
  Source:

int %test1(int %a) {
entry:
       %tmp.1 = add int %a,      123456789      ; <int> [#uses=1]
       %tmp.2 = or  int %tmp.1,  123456789      ; <int> [#uses=1]
       %tmp.3 = xor int %tmp.2,  123456789      ; <int> [#uses=1]
       %tmp.4 = sub int %tmp.3, -123456789      ; <int> [#uses=1]
       ret int %tmp.4
}

Did Emit:

       .machine ppc970


       .text
       .align  2
       .globl  _test1
_test1:
.LBB_test1_0:   ; entry
       addi r2, r3, -13035
       addis r2, r2, 1884
       ori r2, r2, 52501
       oris r2, r2, 1883
       xori r2, r2, 52501
       xoris r2, r2, 1883
       addi r2, r2, 52501
       addis r3, r2, 1883
       blr


Now Emits:

       .machine ppc970


       .text
       .align  2
       .globl  _test1
_test1:
.LBB_test1_0:   ; entry
       lis r2, 1883
       ori r2, r2, 52501
       add r3, r3, r2
       or r3, r3, r2
       xor r3, r3, r2
       add r3, r3, r2
       blr

Patch by Jim Laskey!

llvm-svn: 22749
 2005-08-10 16:34:52 +00:00
Chris Lattner 5f56d71cd7 Fix a bug compiling: select (i32 < i32), f32, f32 
llvm-svn: 22747
 2005-08-10 03:40:09 +00:00
Chris Lattner 54ee86aca7 add a optimization note 
llvm-svn: 22732
 2005-08-09 22:30:57 +00:00
Chris Lattner 6ec7745e80 Update the targets to the new SETCC/CondCodeSDNode interfaces. 
llvm-svn: 22729
 2005-08-09 20:21:10 +00:00