Commit Graph

11286 Commits

Author SHA1 Message Date
Anton Korobeynikov 4218516f5d Lane number should be printed w/o hash
llvm-svn: 78469
2009-08-08 14:05:53 +00:00
Anton Korobeynikov 887d05ce9b Use VLDM / VSTM to spill/reload 128-bit Neon registers
llvm-svn: 78468
2009-08-08 13:35:48 +00:00
Andrew Lenharth e372826523 move this fp select into a pattern
llvm-svn: 78464
2009-08-08 12:49:07 +00:00
Daniel Dunbar 541efcc5c4 llvm-mc/AsmMatcher: Improve match code.
- This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.

llvm-svn: 78461
2009-08-08 07:50:56 +00:00
Bob Wilson e2231070ff Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
2009-08-08 06:13:25 +00:00
Bob Wilson db46af0461 Implement Neon VTRN instructions. For now, anyway, these are selected
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
2009-08-08 05:53:00 +00:00
Evan Cheng 1be453b462 Add a skeleton Thumb2 instruction size reduction pass.
llvm-svn: 78456
2009-08-08 03:21:23 +00:00
Evan Cheng 2aa91cc2be Code refactoring. No functionality change.
llvm-svn: 78455
2009-08-08 03:20:32 +00:00
Evan Cheng 274fcbe43e tADDhirr should target GPR, not tGPR.
llvm-svn: 78454
2009-08-08 03:19:44 +00:00
Evan Cheng 4dc201eb64 I can type.
llvm-svn: 78453
2009-08-08 02:54:37 +00:00
Chris Lattner b94284b5e2 make printInstruction return void since its result is omitted. Make the
error condition get trapped with an assert.

llvm-svn: 78449
2009-08-08 01:32:19 +00:00
Chris Lattner b1692dc267 don't check the result of printInstruction anymore.
llvm-svn: 78444
2009-08-08 00:05:42 +00:00
Anton Korobeynikov 674ffc1e59 Do not generate 32-bit call on win64 when imm does not fit
llvm-svn: 78443
2009-08-07 23:59:21 +00:00
David Goodwin 742db6a6d4 Make NEON single-precision FP support the default for cortex-a8 (again).
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
Chris Lattner e35472e3a9 remove a bunch of now-dead crud from the asmprinter and TAI interfaces.
llvm-svn: 78428
2009-08-07 23:16:27 +00:00
Anton Korobeynikov d28a26dfab Unbreak the stuff
llvm-svn: 78425
2009-08-07 22:51:13 +00:00
Andrew Lenharth a190c169bf avoid this libcall with long inline expansion
llvm-svn: 78420
2009-08-07 22:37:20 +00:00
Anton Korobeynikov 23b28cb824 2 more vdup.32 cases
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
Evan Cheng fb93be2b6f A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.
llvm-svn: 78418
2009-08-07 22:36:37 +00:00
Bill Wendling fe3bdb4b6f Reformatting of lines. Put multiple DEBUG statements under one DEBUG statement.
llvm-svn: 78411
2009-08-07 21:33:25 +00:00
Evan Cheng 6e130db3b7 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
Daniel Dunbar 15b8037034 llvm-mc/AsmMatcher: Tweaks in response to feedback.
llvm-svn: 78404
2009-08-07 20:33:39 +00:00
Evan Cheng b64ec07ea6 This is done.
llvm-svn: 78399
2009-08-07 19:34:52 +00:00
Evan Cheng f0237b1aa6 Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
llvm-svn: 78398
2009-08-07 19:34:35 +00:00
Evan Cheng 4c3b1ca5a0 Fix support to use NEON for single precision fp math.
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Sanjiv Gupta 54c847cd6c Minor fixes to avoid using invalid debugloc.
llvm-svn: 78383
2009-08-07 11:00:02 +00:00
Benjamin Kramer 24ee4d0aa4 Simplify code and avoid allocations.
llvm-svn: 78382
2009-08-07 10:42:28 +00:00
Daniel Dunbar cf18d6befb Improve disabling of X86 AsmMatcher.
llvm-svn: 78381
2009-08-07 09:06:38 +00:00
Daniel Dunbar 32d0bb4c4e Disable X86 AsmMatcher for now, it is causing gcc-4.0 to run out of memory on
i386-apple-darwin9. This presumably will get fixed once the generated code
improves.

llvm-svn: 78379
2009-08-07 08:45:03 +00:00
Daniel Dunbar e10787e710 llvm-mc/AsmMatcher: Move to a slightly more sane matching design.
- Still not very sane, but a least its not 60k lines on X86. :)

 - In terms of correctness, currently some things are hard wired for X86, and we
   still don't properly resolve ambiguities (this is ignoring the instructions
   we don't even match due to funny .td stuff or other corner cases).

The high level changes:
 1. Represent tokens which are significant for matching explicitly as separate
    operands. This uniformly handles not only the instruction mnemonic, but
    also 'signficiant' syntax like the '*' in "call * ...".

 2. Separate the matching of operands to an instruction from the construction of
    the MCInst. In theory this can be done during matching, but since the number
    of variations is small I think it makes sense to decompose the problems.

 3. Improved a few of the mechanisms to at least successfully flatten / tokenize
    the assembly strings for PowerPC and ARM.

 4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
    moving towards for handling ambiguous instructions. The high-bit is to infer
    a partial ordering of the operand classes (and force the user to specify one
    if we can't) and use that to resolve ambiguities.

llvm-svn: 78378
2009-08-07 08:26:05 +00:00
Evan Cheng 82ff022ed2 Error out, rather than infinite looping, if constant island pass can't converge.
llvm-svn: 78377
2009-08-07 07:35:21 +00:00
Evan Cheng 317bd7aab2 tBfar is bl, which clobbers LR.
llvm-svn: 78370
2009-08-07 05:45:07 +00:00
Sanjiv Gupta 003dc1fa5b Run memsel inserter just before emit assembly to avoid tinkering by other passes.
llvm-svn: 78369
2009-08-07 05:44:27 +00:00
Andrew Lenharth a3a3453acf These should be expanded
llvm-svn: 78365
2009-08-07 02:17:44 +00:00
Dan Gohman a6d0afcb74 Fix a bunch of namespace pollution.
llvm-svn: 78363
2009-08-07 01:32:21 +00:00
Evan Cheng b972e5633f It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
2009-08-07 00:34:42 +00:00
Nicolas Geoffray edfdd07a79 Output the new StructType constructor, which takes the context of the
module as first argument.

llvm-svn: 78340
2009-08-06 21:31:35 +00:00
Devang Patel cd4688905f Use DebugInfoFinder
llvm-svn: 78334
2009-08-06 20:53:24 +00:00
Bob Wilson 0127031c20 Implement Neon VST[234] operations.
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
David Goodwin b062c236c5 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
llvm-svn: 78321
2009-08-06 16:52:47 +00:00
Chris Lattner 1ff90134a4 Fix several fixmes and clean up code by sinking *all* section
creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.

1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
   pure virtual method to assign sections to globals with a specified
   section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
   now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
   They are now all detangled and understandable, woo! :)

llvm-svn: 78319
2009-08-06 16:39:58 +00:00
Chris Lattner b29996eb23 go through PIC16TargetObjectFile to make sections instead of
creating them directly in the pic16 asmprinter.

llvm-svn: 78317
2009-08-06 16:27:28 +00:00
Anton Korobeynikov d0439d0638 We need to sext global addresses in kernel code model, not zext
llvm-svn: 78299
2009-08-06 11:23:24 +00:00
Dan Gohman 130e2c7aed Fix a bug in x86's PreprocessForRMW logic that was exposed
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.

llvm-svn: 78297
2009-08-06 09:22:57 +00:00
Anton Korobeynikov 82db9891fa Missed part of recent kernel codemodel tweaks
llvm-svn: 78293
2009-08-06 09:11:19 +00:00
Bob Wilson 488db94e7b Neon does not actually have VLD{234}.64 instructions.
These operations will have to be synthesized from other instructions.

llvm-svn: 78263
2009-08-06 00:24:27 +00:00
Bob Wilson e148ceaf65 Add a new pre-allocation pass to assign adjacent registers for Neon instructions
that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256
2009-08-05 23:12:45 +00:00
Anton Korobeynikov 741ea0d7fd Better handle kernel code model. Also, generalize the things and fix one
subtle bug with small code model.

llvm-svn: 78255
2009-08-05 23:01:26 +00:00
Dan Gohman 77f33b71c7 Use GR32 for copies between GR32_NOSP and GR32_NOREX, as neither
is a subset of the other, but both are subsets of GR32.

llvm-svn: 78250
2009-08-05 22:18:26 +00:00
David Goodwin e5b5d8fbb3 When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
llvm-svn: 78244
2009-08-05 21:02:22 +00:00