d59e640455
AMDGPU: Improve nsw/nuw/exact when promoting uniform i16 ops
...
These were simply preserving the flags of the original operation,
which was too conservative in most cases and incorrect for mul.
nsw/nuw may be needed for some combines to cleanup messes when
intermediate sext_inregs are introduced later.
Tested valid combinations with alive.
llvm-svn: 293776
2017-02-01 16:25:23 +00:00
269ffdac4e
AMDGPU: Fix crash on i16 constant expression
...
llvm-svn: 288861
2016-12-06 23:18:06 +00:00
f74fc60a7d
[AMDGPU] Promote uniform (i1, i16] operations to i32
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Differential Revision: https://reviews.llvm.org/D25302
llvm-svn: 283555
2016-10-07 14:22:58 +00:00
b4eb5d5049
[AMDGPU] Promote uniform i16 bitreverse intrinsic to i32
...
Differential Revision: https://reviews.llvm.org/D25121
llvm-svn: 283415
2016-10-06 02:20:46 +00:00
691e2e020b
[AMDGPU] Sign extend AShr when promoting (instead of zero extending)
...
llvm-svn: 283130
2016-10-03 18:29:01 +00:00
e14df4b236
[AMDGPU] Promote uniform i16 ops to i32 ops for targets that have 16 bit instructions
...
Differential Revision: https://reviews.llvm.org/D24125
llvm-svn: 282624
2016-09-28 20:05:39 +00:00
Matt Arsenault