fe58ca3218
[Hexagon] Remove unused .td files
...
llvm-svn: 294775
2017-02-10 19:54:00 +00:00
a72fad980c
[Hexagon] Replace instruction definitions with auto-generated ones
...
llvm-svn: 294753
2017-02-10 15:33:13 +00:00
49ffff12e5
[RDF] Extract the physical register information into a separate class
...
llvm-svn: 293510
2017-01-30 17:46:56 +00:00
c8b943860f
[Hexagon] Add Hexagon-specific loop idiom recognition pass
...
llvm-svn: 293213
2017-01-26 21:41:10 +00:00
39d14f3bc3
Reapply r286080 with a phony change in Hexagon's CMakeLists.txt
...
Cmake has not recognized that Hexagon.td has a new dependency in
HexagonPatterns.td. All changes to that file were not visible to
the build bots.
llvm-svn: 286084
2016-11-06 20:55:57 +00:00
a77fe4eef3
[RDF] Replace RegisterAliasInfo with target-independent code using lane masks
...
llvm-svn: 283122
2016-10-03 17:14:48 +00:00
12e03aa5fe
[Hexagon] Delete HexagonSelectCCInfo.td
...
This file is not used. The location assignment of call arguments and
return values is implemented directly in HexagonISelLowering.
llvm-svn: 278237
2016-08-10 16:23:53 +00:00
8123b966cb
[Hexagon] Generate vector printing instructions
...
llvm-svn: 277370
2016-08-01 19:36:39 +00:00
e95e95521c
[Hexagon] Implement DFA based hazard recognizer
...
The post register allocator scheduler can generate poor schedules
because the scoreboard hazard recognizer is unable to identify
hazards for Hexagon precisely. Instead, Hexagon should use a DFA
based hazard recognizer.
Patch by Brendon Cahoon.
llvm-svn: 277143
2016-07-29 13:59:09 +00:00
167d918225
[Hexagon] Implement MI-level constant propagation
...
llvm-svn: 277028
2016-07-28 20:01:59 +00:00
2eec13680e
Touch Hexagon/CMakeLists.txt to regenerate build files, since r268641 complains of missing HexagonAlias.td on ninja.
...
FIXME: TableGen.cmake globs *.td(s) with wildcards for deps. It is not good.
llvm-svn: 268666
2016-05-05 19:28:01 +00:00
f5cbac93eb
[Hexagon] Optimize addressing modes for load/store
...
Patch by Jyotsna Verma.
llvm-svn: 268051
2016-04-29 15:49:13 +00:00
7b59ae28aa
[Hexagon] Implement branch relaxation
...
Patch by Sirish Pande.
llvm-svn: 266792
2016-04-19 18:30:18 +00:00
7793ddb043
[Hexagon] Optimize stack slot spills
...
Replace spills to memory with spills to registers, if possible. This
applies mostly to predicate registers (both scalar and vector), since
they are very limited in number. A spill of a predicate register may
happen even if there is a general-purpose register available. In cases
like this the stack spill/reload may be eliminated completely.
This optimization will consider all stack objects, regardless of where
they came from and try to match the live range of the stack slot with
a dead range of a register from an appropriate register class.
llvm-svn: 260758
2016-02-12 22:53:35 +00:00
7ce3dbcb57
[Hexagon] Remove HexagonExpandPredSpillCode pass
...
This code is dead. The expansion is now done in HexagonFrameLowering.
llvm-svn: 260691
2016-02-12 17:09:58 +00:00
1279881315
[Hexagon] Implement RDF-based post-RA optimizations
...
- Handle simple cases of register copies (what current RDF CP allows).
- Hexagon-specific dead code elimination: handles dead address updates
in post-increment instructions.
llvm-svn: 257504
2016-01-12 19:09:01 +00:00
c09d630e50
RDF: Copy propagation
...
This is a very limited implementation of DFG-based copy propagation.
It only handles actual COPY instructions (does not handle other equivalents
such as add-immediate with a 0 operand).
The major limitation is that it does not update the DFG: that will be the
change required to make it more robust (hopefully coming up soon).
llvm-svn: 257490
2016-01-12 17:23:48 +00:00
6f4000e763
RDF: Dead code elimination
...
Utility class to perform DFG-based dead code elimination.
llvm-svn: 257485
2016-01-12 17:01:16 +00:00
acdff46a9c
RDF: Implement register liveness analysis
...
Compute block live-ins and operand kill flags from the DFG.
llvm-svn: 257480
2016-01-12 15:56:33 +00:00
b5b5a1d7ad
Register Data Flow: data flow graph
...
Target independent, SSA-based data flow framework for representing
data flow between physical registers.
This commit implements the creation of the actual data flow graph.
llvm-svn: 257477
2016-01-12 15:09:49 +00:00
7cd0892729
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
...
llvm-svn: 252443
2015-11-09 04:07:48 +00:00
ced9941cd4
[Hexagon] Bit-based instruction simplification
...
Analyze bit patterns of operands and values of instructions to perform
various simplifications, dead/redundant code elimination, etc.
llvm-svn: 250868
2015-10-20 22:57:13 +00:00
055c5fd74e
[Hexagon] Remove unnecessary argument sign extends
...
llvm-svn: 250724
2015-10-19 19:10:48 +00:00
a7c5f0409c
[Hexagon] Split double registers
...
llvm-svn: 250549
2015-10-16 20:38:54 +00:00
aec39c68ae
[Hexagon] Delete lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
...
llvm-svn: 250543
2015-10-16 19:51:53 +00:00
5b7dd0cdf9
[Hexagon] Merge adjacent stores
...
llvm-svn: 250542
2015-10-16 19:43:56 +00:00
fb33824efd
[Hexagon] Add an early if-conversion pass
...
llvm-svn: 249423
2015-10-06 15:49:14 +00:00
73e66f323a
[Hexagon] Implement TargetTransformInfo for Hexagon
...
Author: Brendon Cahoon <bcahoon@codeaurora.org>
llvm-svn: 244089
2015-08-05 18:35:37 +00:00
921722049d
[Hexagon] Generate MUX from conditional transfers when dot-new not possible
...
llvm-svn: 242711
2015-07-20 21:23:25 +00:00
758744706a
[Hexagon] Generate instructions for operations on predicate registers
...
Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.
llvm-svn: 242186
2015-07-14 19:30:21 +00:00
a0ecf07c0b
[Hexagon] Generate "extract" instructions more aggressively
...
Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.
llvm-svn: 242163
2015-07-14 17:07:24 +00:00
79b2433e7c
[Hexagon] Implement commoning of GetElementPtr instructions
...
llvm-svn: 241714
2015-07-08 19:22:28 +00:00
21b53a5120
[Hexagon] Generate "insert" instructions more aggressively
...
llvm-svn: 241683
2015-07-08 14:47:34 +00:00
d19b4767ff
Revert 241681: causes Windows builds to fail
...
llvm-svn: 241682
2015-07-08 14:34:13 +00:00
712b15b45e
[Hexagon] Generate "insert" instructions more aggressively
...
llvm-svn: 241681
2015-07-08 14:22:27 +00:00
e53b31a593
[Hexagon] Implement bit-tracking facility with specifics for Hexagon
...
This includes code that is intended to be target-independent as well
as the Hexagon-specific details. This is just the framework without
any users.
llvm-svn: 241595
2015-07-07 15:16:42 +00:00
c05dff1792
Expand MUX instructions early on Hexagon
...
This time with all files included.
llvm-svn: 233696
2015-03-31 13:35:12 +00:00
8c4fd2bdeb
Revert 233694. Weak SVN-fu.
...
llvm-svn: 233695
2015-03-31 13:32:32 +00:00
261d62c862
Expand MUX instructions early on Hexagon
...
llvm-svn: 233694
2015-03-31 13:29:17 +00:00
4683395808
Hexagon: Remove pass that does nothing at all
...
llvm-svn: 231791
2015-03-10 15:06:38 +00:00
241a9e8db2
Update CMake build for removed files.
...
llvm-svn: 227834
2015-02-02 18:52:49 +00:00
ff06261aed
[Hexagon] [NFC] Merging InstPrinter directory in to MCTargetDesc since they have a circular dependency.
...
llvm-svn: 222458
2014-11-20 21:56:35 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
...
Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
816ef086f6
[Hexagon] [NFC] Alphabetizing cmake files.
...
llvm-svn: 221370
2014-11-05 17:38:48 +00:00
5241881bbc
[Hexagon] Reverting 220584 to address ASAN errors.
...
llvm-svn: 221210
2014-11-04 00:14:36 +00:00
838307b31f
[Hexagon] Resubmission of 220427
...
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220584
2014-10-24 19:00:32 +00:00
bd20251a4a
[CMake] Prune CRLF in CMakeLists.txt(s).
...
llvm-svn: 220480
2014-10-23 11:31:50 +00:00
88ebb9e2da
[Hexagon] Adding basic disassembler.
...
Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc
llvm-svn: 220393
2014-10-22 16:49:14 +00:00
7da3f9acba
Adding skeleton for unit testing Hexagon Code Emission
...
Adding and modifying CMakeLists.txt files to run unit tests under
unittests/Target/* if the directory exists. Adding basic unit test to check
that code emitter object can be retrieved.
Differential Revision: http://reviews.llvm.org/D5523
Change by: Colin LeMahieu
llvm-svn: 218986
2014-10-03 13:18:11 +00:00
226e10edff
[CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.
...
I think, in principle, intrinsics_gen may be added explicitly.
That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen.
Almost all source files depend on both CommonTaleGen and intrinsics_gen.
Explicit add_dependencies() have been pruned under lib/Target.
llvm-svn: 195929
2013-11-28 17:04:31 +00:00
Krzysztof Parzyszek