02650ac036
[SVE][CodeGen] Add README for SVE-related warnings in tests
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I have added a new file:
llvm/test/CodeGen/AArch64/README
that describes what to do in the event one of the SVE codegen tests
fails the warnings check. In addition, I've added comments to all
the relevant SVE tests pointing users at the README file.
Differential Revision: https://reviews.llvm.org/D83467
2020-07-14 08:31:10 +01:00
edcfef8fee
[AArch64][SVE] Add bfloat16 support to store intrinsics
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Summary:
Bfloat16 support added for the following intrinsics:
- ST1
- STNT1
Reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm
Reviewed By: fpetrogalli
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D82448
2020-06-26 11:05:56 +01:00
0ccfe1b267
[AArch64][SVE] Predicate bfloat16 load patterns with HasBF16
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Reviewers: sdesmalen, c-rhodes, efriedma, fpetrogalli
Reviewed By: fpetrogalli
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82464
2020-06-26 10:38:24 +01:00
3d6cab271c
[AArch64][SVE] Add bfloat16 support to load intrinsics
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Summary:
Bfloat16 support added for the following intrinsics:
- LD1
- LD1RQ
- LDNT1
- LDNF1
- LDFF1
Reviewers: sdesmalen, c-rhodes, efriedma, stuij, fpetrogalli, david-arm
Reviewed By: fpetrogalli
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D82298
2020-06-24 10:32:19 +01:00
bd97342a0c
[CodeGen] Let computeKnownBits do something sensible for scalable vectors
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Until we have a real need for computing known bits for scalable
vectors I have simply changed the code to bail out for now and
pretend we know nothing. I've also fixed up some simple callers of
computeKnownBits too.
Differential Revision: https://reviews.llvm.org/D80437
2020-06-11 08:17:11 +01:00
5c2c94648e
[AArch64][SVE] Implement masked store intrinsics
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Summary:
Adds support for codegen of masked stores, with non-truncating
and truncating variants.
Reviewers: huntergr, greened, dmgreen, rovka, sdesmalen
Reviewed By: dmgreen, sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69378
2019-10-30 11:56:54 +00:00
da720a38b9
[AArch64][SVE] Implement masked load intrinsics
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Summary:
Adds support for codegen of masked loads, with non-extending,
zero-extending and sign-extending variants.
Reviewers: huntergr, rovka, greened, dmgreen
Reviewed By: dmgreen
Subscribers: dmgreen, samparker, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68877
2019-10-28 10:06:14 +00:00
David Sherwood