8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
9340ea59e1
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
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This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
c5327226e4
Encode the Caml frametable by following what the comment says: the number of descriptors
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is first emitted, and StackOffsets are emitted in 16 bits.
llvm-svn: 104488
2010-05-24 12:24:11 +00:00
6738a2e39e
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104467
2010-05-23 18:36:38 +00:00
8271d1bb4a
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104466
2010-05-23 18:36:34 +00:00
3ff1a06de6
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
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llvm-svn: 104463
2010-05-23 17:44:06 +00:00
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
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llvm-svn: 104455
2010-05-23 05:42:31 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
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llvm-svn: 104435
2010-05-22 06:37:33 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
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llvm-svn: 104421
2010-05-22 01:47:14 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
6fdea1bda8
Add full bss data support for darwin tls variables.
...
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
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llvm-svn: 104412
2010-05-22 00:04:14 +00:00
61438fe064
Clean up extra whitespace.
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llvm-svn: 104410
2010-05-21 23:53:55 +00:00
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
4dc833c607
add a note
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llvm-svn: 104404
2010-05-21 23:16:21 +00:00
09d47031b1
Expand on comment.
...
llvm-svn: 104396
2010-05-21 23:03:53 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
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llvm-svn: 104394
2010-05-21 23:01:38 +00:00
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
...
llvm-svn: 104385
2010-05-21 21:22:19 +00:00
3dca28d0e2
Fix section attribute name.
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llvm-svn: 104381
2010-05-21 21:08:52 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
7d7f604321
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
llvm-svn: 104372
2010-05-21 20:02:01 +00:00
1782aae355
Simplify
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llvm-svn: 104338
2010-05-21 18:49:09 +00:00
2b78565842
Previous commit message should refer to 104308.
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llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
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llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
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llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
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llvm-svn: 104326
2010-05-21 17:49:07 +00:00
a81e1cab04
constify accessor.
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llvm-svn: 104325
2010-05-21 17:47:50 +00:00
b4e1687270
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
llvm-svn: 104323
2010-05-21 17:36:32 +00:00
8e8e090301
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
llvm-svn: 104322
2010-05-21 16:42:30 +00:00
a648c6a757
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
llvm-svn: 104321
2010-05-21 16:36:13 +00:00
1f3801062d
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
llvm-svn: 104320
2010-05-21 16:32:16 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
ec9d6faef0
Add support for parsing the ELF .type assembler directive.
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llvm-svn: 104316
2010-05-21 11:36:59 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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llvm-svn: 104307
2010-05-21 00:43:17 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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llvm-svn: 104306
2010-05-21 00:42:32 +00:00
fbd6c45e06
Simplify.
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llvm-svn: 104302
2010-05-21 00:10:20 +00:00
c120ffe3f6
Fix __crashreport_info__ declaration.
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llvm-svn: 104300
2010-05-20 23:50:19 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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llvm-svn: 104293
2010-05-20 23:26:43 +00:00
9b48b856ea
DominatorTree.getNode can return null for unreachable blocks.
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llvm-svn: 104290
2010-05-20 22:46:54 +00:00
86110fa2bb
Minor code cleanups.
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llvm-svn: 104287
2010-05-20 22:25:20 +00:00
3a48292204
Print a space after the colon.
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llvm-svn: 104279
2010-05-20 21:11:37 +00:00
6295f2ebb8
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
a4ca28a3ae
Add comments.
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llvm-svn: 104276
2010-05-20 20:52:00 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
0adee9b362
Rename variable. add comment.
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llvm-svn: 104274
2010-05-20 20:35:24 +00:00
927bcaadda
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
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llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
4c4043cf34
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
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Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
llvm-svn: 104269
2010-05-20 20:05:31 +00:00
8ec018cedf
Add some comments.
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llvm-svn: 104268
2010-05-20 20:00:41 +00:00
8ce95cc3c5
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
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llvm-svn: 104267
2010-05-20 20:00:25 +00:00
490c8ab76d
Refactor.
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llvm-svn: 104265
2010-05-20 19:57:06 +00:00
141791c6d1
Grammar fix. This is a test commit.
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llvm-svn: 104264
2010-05-20 19:45:09 +00:00
ab5fb7f559
Minor code cleanups.
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llvm-svn: 104263
2010-05-20 19:44:23 +00:00
ee2fea3cd7
When canonicalizing icmp operand order to put the loop invariant
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operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
llvm-svn: 104262
2010-05-20 19:26:52 +00:00
3e69aa0399
llvmc: Make segfault detection work on Win32.
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llvm-svn: 104261
2010-05-20 19:23:47 +00:00
fdf9874ba7
Set Changed to true when canonicalizing ICmp operand order; even though
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it isn't a very interesting change, it's a change nonetheless.
llvm-svn: 104260
2010-05-20 19:16:03 +00:00
5954994bba
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
63d4f68df4
Remove dbg_value workaround and associated command line option
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llvm-svn: 104254
2010-05-20 18:34:01 +00:00
098a47931c
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
d7d6638e3e
The PPC MFCR instruction implicitly uses all 8 of the CR
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registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
e2ff7f3a7d
Strip llvm.dbg.lv also.
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llvm-svn: 104236
2010-05-20 16:49:22 +00:00
981563d0ba
Rename a variable to avoid shadowing.
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llvm-svn: 104234
2010-05-20 16:41:11 +00:00
e1c53f29d3
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
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llvm-svn: 104233
2010-05-20 16:36:41 +00:00
6b733fc189
Minor code simplification.
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llvm-svn: 104232
2010-05-20 16:23:28 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
5238275478
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
80a9608442
Move the code for deleting BaseRegs and LSRUses into helper functions,
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and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
llvm-svn: 104225
2010-05-20 15:17:54 +00:00
7c3e230cd1
Reduce string trashing.
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llvm-svn: 104223
2010-05-20 14:14:22 +00:00
bdd062dae0
Add a hybrid bottom up scheduler that reduce register usage while avoiding
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pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
c53cc4f8bf
Fix typo in comment.
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llvm-svn: 104209
2010-05-20 03:30:09 +00:00
1e19eab963
Define the x86 pause instruction.
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llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
27e7ffc7d4
Partial code for emitting thread local bss data.
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llvm-svn: 104197
2010-05-20 00:49:07 +00:00
20fab456da
Teach LSR how to cope better with unrolled loops on targets where
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the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
llvm-svn: 104186
2010-05-19 23:43:12 +00:00
42603958fb
Optimize away insertelement of an undef value. This shows up in
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
7cbfa4462f
fix rdar://7986634 - match instruction opcodes case insensitively.
...
llvm-svn: 104183
2010-05-19 23:34:33 +00:00
f98511473e
Enable preserving debug information through post-RA scheduling
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llvm-svn: 104175
2010-05-19 22:57:47 +00:00
604560c5fe
Fix the post-RA instruction scheduler to handle instructions referenced by
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more than one dbg_value instruction. rdar://7759363
llvm-svn: 104174
2010-05-19 22:57:06 +00:00
70e506e18a
Code clean up.
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llvm-svn: 104173
2010-05-19 22:42:23 +00:00
a08130864e
Revert r104165.
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llvm-svn: 104172
2010-05-19 21:58:28 +00:00
e0eddb21f5
Add support for partial redefs to the fast register allocator.
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A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
llvm-svn: 104167
2010-05-19 21:36:05 +00:00
0fe341e2e2
There is no need to maintain InsnsBeginScopeSet separately.
...
llvm-svn: 104165
2010-05-19 21:26:53 +00:00
5d4c134a94
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
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partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
llvm-svn: 104149
2010-05-19 20:36:22 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
...
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
e11cdf8cc8
TwoAddressInstructionPass doesn't really know how to merge live intervals when
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lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
llvm-svn: 104146
2010-05-19 20:08:00 +00:00
59a61fd7cc
llvmc: report an error if a child process segfaults.
...
llvm-svn: 104145
2010-05-19 19:24:32 +00:00
6a1bfd282b
When expanding a vector_shuffle, the element type may not be legal and may
...
need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
llvm-svn: 104141
2010-05-19 18:48:32 +00:00
52e37becf6
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
...
llvm-svn: 104122
2010-05-19 17:20:58 +00:00
d2f78e755f
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
llvm-svn: 104120
2010-05-19 15:26:43 +00:00
b243dfb085
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
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CALL64pcrel32, for the same reason.
llvm-svn: 104116
2010-05-19 08:07:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
...
llvm-svn: 104114
2010-05-19 07:26:50 +00:00
4f6c7c6d94
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
...
llvm-svn: 104112
2010-05-19 06:20:44 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
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llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
...
avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
744c96dd48
Add a comment explaining why this code uses Append mode.
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llvm-svn: 104095
2010-05-19 01:21:34 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
...
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
beebef4137
Add a comment.
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llvm-svn: 104089
2010-05-18 23:55:57 +00:00
50f8f2c23d
Fix the predicate which checks for non-sensical formulae which have
...
constants in registers which partially cancel out their immediate fields.
llvm-svn: 104088
2010-05-18 23:48:08 +00:00
4cf99b5303
Factor out the code for recomputing an LSRUse's Regs set after some
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of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
llvm-svn: 104087
2010-05-18 23:42:37 +00:00
055c01d9dc
Fix a crash when debugging the coalescer. DebugValue instructions are not
...
in the coalescer's instruction map.
llvm-svn: 104086
2010-05-18 23:19:42 +00:00
a4eca05174
Factor out code for estimating search space complexity into a helper
...
function.
llvm-svn: 104082
2010-05-18 22:51:59 +00:00
63e9015248
Add some more debug output.
...
llvm-svn: 104080
2010-05-18 22:41:32 +00:00
f1c7b1b42f
Factor out the code for deleting a formula from an LSRUse into
...
a helper function.
llvm-svn: 104079
2010-05-18 22:39:15 +00:00
8aca7ef903
Make some debug output more informative.
...
llvm-svn: 104078
2010-05-18 22:37:37 +00:00
06ab08f795
Print an error message in Formula::print if the HasBaseReg flag
...
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
llvm-svn: 104077
2010-05-18 22:35:55 +00:00
248c41d108
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
...
confusion with LSRInstance's RegUses member.
llvm-svn: 104076
2010-05-18 22:33:00 +00:00
430b6e40ab
Remember to update VirtRegLastUse when spilling without killing before a call.
...
llvm-svn: 104074
2010-05-18 22:20:09 +00:00
f8bf663873
Teach mode load folding and unfolding code about CMP32ri8 and friends.
...
llvm-svn: 104068
2010-05-18 21:54:15 +00:00
4ed63f8687
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
...
specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
887dd1cd31
When converting a test to a cmp to fold a load, use the cmp that has an
...
8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
9f46539e07
make mcinstlower remove all but the first operand to CALL64pcrel32.
...
The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
...
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
feedc90c57
Implement EmitTBSSSymbol for MachOStreamer.
...
Fixes build failure as well.
llvm-svn: 104059
2010-05-18 21:26:41 +00:00
5c87be766d
Make EmitTBSSSymbol take a section argument so that we can find it later.
...
Fix up callers and users.
llvm-svn: 104057
2010-05-18 21:16:04 +00:00
663543b4d7
Properly handle multiple definitions of a virtual register in the same
...
instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
llvm-svn: 104056
2010-05-18 21:10:50 +00:00
45b3f702ab
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
...
llvm-svn: 104051
2010-05-18 20:07:47 +00:00
e7fc64a5c9
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
...
llvm-svn: 104050
2010-05-18 20:03:28 +00:00
7bcc9e9450
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
...
CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
llvm-svn: 104039
2010-05-18 18:09:20 +00:00
53e0631516
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
...
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
llvm-svn: 104038
2010-05-18 17:51:35 +00:00
4843178d6b
Teach the machine code verifier to use getSubRegisterRegClass().
...
The old approach was wrong. It had an off-by-one error.
llvm-svn: 104034
2010-05-18 17:31:12 +00:00
d5563f420a
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
...
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
llvm-svn: 104033
2010-05-18 17:28:24 +00:00
f16c12d7a1
MC/Mach-O: Remove some FIXMEs.
...
llvm-svn: 104032
2010-05-18 17:28:20 +00:00
39617bb08a
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
...
llvm-svn: 104031
2010-05-18 17:28:17 +00:00
a4820fcc78
MC/X86: Implement custom lowering to make sure we match things like
...
X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
llvm-svn: 104030
2010-05-18 17:22:24 +00:00
62bc96a1a5
llc (et al): Add support for --show-encoding and --show-inst.
...
llvm-svn: 104029
2010-05-18 17:22:19 +00:00
dea5310433
Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream.
...
Update the comment.
llvm-svn: 104021
2010-05-18 15:25:14 +00:00
ab7be75e3f
Simplify MCContext::(Next|Get)Instance
...
- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.
llvm-svn: 104020
2010-05-18 12:15:34 +00:00
48f0de96d6
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
...
llvm-svn: 104004
2010-05-18 00:03:40 +00:00
93d8844699
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
...
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
llvm-svn: 103995
2010-05-17 23:29:23 +00:00
1e4f55200d
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
...
llvm-svn: 103994
2010-05-17 23:24:12 +00:00
02d3368831
- Set the "HasCalls" flag after instruction selection is finished.
...
- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00
0510b48fd9
Added support in MC for Directional Local Labels.
...
llvm-svn: 103989
2010-05-17 23:08:19 +00:00
9635b3da6b
More data/parsing support for tls directives. Add a few more testcases
...
and cleanup comments as well.
llvm-svn: 103985
2010-05-17 22:53:55 +00:00
f2c9a96f3c
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
...
llvm-svn: 103984
2010-05-17 22:09:49 +00:00
cd04ed3533
vmov of immediates are trivially re-materializable.
...
llvm-svn: 103982
2010-05-17 21:54:50 +00:00
bb166bed40
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
...
llvm-svn: 103981
2010-05-17 21:54:30 +00:00
ce5e1bb326
MC: Add dyn_cast support to MCSection.
...
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.
llvm-svn: 103980
2010-05-17 21:54:26 +00:00
b7b796cc11
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
...
- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
llvm-svn: 103979
2010-05-17 21:19:59 +00:00
585792738b
Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.
...
This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.
llvm-svn: 103975
2010-05-17 21:02:08 +00:00
bf79238599
Add some section and constant support for darwin TLS.
...
llvm-svn: 103974
2010-05-17 21:02:07 +00:00
29c463862e
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
...
llvm-svn: 103971
2010-05-17 20:57:12 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
0211a96989
MC/Mach-O: Fix some differences in symbol flag handling.
...
- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
llvm-svn: 103964
2010-05-17 20:12:31 +00:00
70563bbba5
Remove debug option. Add comment on spill order determinism.
...
llvm-svn: 103961
2010-05-17 20:01:22 +00:00
3d98b996ff
Turn on -neon-reg-sequence by default.
...
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
2010-05-17 19:51:20 +00:00
9b4a824217
llvm-mc: Support reassignment of variables in one special case, when the
...
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
llvm-svn: 103950
2010-05-17 17:46:23 +00:00
176a9c4272
Avoid allocating the same physreg to multiple virtregs in one instruction.
...
While that approach works wonders for register pressure, it tends to break
everything.
This should unbreak the arm-linux builder and fix a number of miscompilations.
llvm-svn: 103946
2010-05-17 17:18:59 +00:00
f5e8c86424
Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map.
...
llvm-svn: 103940
2010-05-17 15:30:37 +00:00
6649cdaa23
Extract spill cost calculation to a new method, and use definePhysReg() to clear
...
out aliases when allocating. Clean up allocVirtReg().
Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.
llvm-svn: 103939
2010-05-17 15:30:32 +00:00
188855abef
Remove unused member variable.
...
llvm-svn: 103936
2010-05-17 09:47:55 +00:00
7d22a81b61
Only use clairvoyance when defining a register, and then only if it has one use.
...
This makes allocation independent on the ordering of use-def chains.
llvm-svn: 103935
2010-05-17 04:50:57 +00:00
f915d14955
Eliminate a hash table probe when killing virtual registers.
...
llvm-svn: 103934
2010-05-17 03:26:09 +00:00
edd3d9db13
Execute virtreg kills immediately instead of after processing all uses.
...
This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.
llvm-svn: 103933
2010-05-17 03:26:06 +00:00
e07a408afc
Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
...
llvm-svn: 103931
2010-05-17 02:49:21 +00:00
1069a09691
Now that we don't keep live registers across calls, there is not reason to go
...
through the very long list of call-clobbered registers. We just assume all
registers are clobbered.
llvm-svn: 103930
2010-05-17 02:49:18 +00:00
397068de06
Boldly attempt consistent capitalization. Functional changes unintended.
...
llvm-svn: 103929
2010-05-17 02:49:15 +00:00
68b1bbe66a
Assume that we'll handle mangling the symbols earlier and just put the
...
symbol to the file as we have it. Simplifies out tbss handling.
llvm-svn: 103928
2010-05-17 02:13:02 +00:00
8044c989d1
Spill and kill all virtual registers across a call.
...
Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.
llvm-svn: 103927
2010-05-17 02:07:32 +00:00
d2ef1fbc82
Reduce hashtable probes by using DenseMap::insert() for lookup.
...
llvm-svn: 103926
2010-05-17 02:07:29 +00:00
fb43e065a4
Make MBB a class member instead of passing it around everywhere.
...
llvm-svn: 103925
2010-05-17 02:07:22 +00:00
166a7993ba
Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
...
llvm-svn: 103922
2010-05-17 01:47:47 +00:00
5a2809cbd8
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
...
llvm-svn: 103917
2010-05-17 01:11:46 +00:00
2ef974ee0e
Revert 103911; it broke a test that expects bitconvert
...
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
llvm-svn: 103914
2010-05-16 20:19:04 +00:00
fc1492d71b
Make x86-64 64-bit bitconvert work when SSE is not available.
...
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
llvm-svn: 103911
2010-05-16 18:22:38 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
8f35fabbc1
Add support for thiscall calling convention.
...
Patch by Charles Davis and Steven Watanabe!
llvm-svn: 103902
2010-05-16 09:08:45 +00:00
4c719c4515
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
...
llvm-svn: 103901
2010-05-16 08:54:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
...
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
...
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
bb4656c05e
Improve assertion messages.
...
llvm-svn: 103882
2010-05-15 18:38:02 +00:00
1bf28a128b
Some cheap DAG combine goodness for multiplication with a particular constant.
...
This can be extended later on to handle more "complex" constants.
llvm-svn: 103881
2010-05-15 18:16:59 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
9e01b615a4
improve portability to systems that don't have round, patch by
...
Evzen Muller!
llvm-svn: 103877
2010-05-15 17:11:55 +00:00
93cd0f1c89
improve portability to systems that don't have powf/modf (e.g. solaris 9)
...
patch by Evzen Muller!
llvm-svn: 103876
2010-05-15 17:10:24 +00:00
75142e6bfc
Fix an GCC warning that seems to have actually caught a bug (!!!) in
...
a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.
llvm-svn: 103869
2010-05-15 10:23:23 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
...
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
84ce290822
Calculate liveness on the fly for local registers.
...
When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.
This makes the fast allocator independent of incoming kill flags.
llvm-svn: 103866
2010-05-15 06:09:08 +00:00
b35818eb25
Teach the always inliner to release its inline cost estimates, like the basic
...
inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?
llvm-svn: 103858
2010-05-15 04:26:25 +00:00
002a45eb64
Clean up, no functional change.
...
llvm-svn: 103857
2010-05-15 03:41:58 +00:00
3d214cdfaf
v4i64 and v8i64 are only synthesizable when NEON is available.
...
llvm-svn: 103855
2010-05-15 02:20:21 +00:00
4cad68eb34
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
...
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
2010-05-15 02:18:07 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
...
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
e26e56e72b
A partial re-def instruction may be a copy.
...
llvm-svn: 103850
2010-05-15 01:35:44 +00:00
8c2d062ea6
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
...
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-14 23:21:14 +00:00
Jakob Stoklund Olesen