c36b1f35f0
Add basic error checking to MemoryBuffer::getSTDIN.
...
llvm-svn: 104855
2010-05-27 17:31:51 +00:00
ece4bf5148
Use the return value of getMagicNumber instead of using a
...
separate canRead() call.
llvm-svn: 104853
2010-05-27 17:18:38 +00:00
78d1e84521
Don't bother clearing the Magic string when the magic number
...
can't be read, since it isn't cleared on other error paths.
llvm-svn: 104852
2010-05-27 17:14:10 +00:00
16f4bd8140
Don't bother checking canRead() before calling getMagicNumber();
...
getMagicNumber() does its own error checking.
llvm-svn: 104851
2010-05-27 17:12:23 +00:00
5e6b71ce34
inlined function's arguments need a label to mark the start point because they are not directly attached to current function.
...
llvm-svn: 104848
2010-05-27 16:47:30 +00:00
8e99e50d08
Support for nested functions/classes in debug output. Radar 7424645.
...
llvm-svn: 104841
2010-05-27 16:16:54 +00:00
eaddfac539
Rearrange conditionals so we don't get caught with the correct type as wrong.
...
llvm-svn: 104793
2010-05-27 00:52:31 +00:00
6b9a9fe207
Simplify. Eliminate unneeded debug_loc entry.
...
llvm-svn: 104785
2010-05-26 23:55:23 +00:00
d67defdfe2
Avoid counting InlineAsm as a call - it prevents loop unrolling.
...
PR7026
Patch by Pekka Jääskeläinen!
llvm-svn: 104780
2010-05-26 22:40:28 +00:00
084bcb1322
Fix Lint printing warnings multiple times. Remove the ErrorStr
...
option from lintModule, which was an artifact from being
based on Verifier code.
llvm-svn: 104765
2010-05-26 22:28:53 +00:00
c0b69020cd
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
...
to be matched.
llvm-svn: 104757
2010-05-26 22:21:28 +00:00
a20a5cd24f
Reinstate checking of stackrestore, with checking for both Read
...
and Write, and add a comment explaining this.
llvm-svn: 104756
2010-05-26 22:21:25 +00:00
4f6da9e3a8
Give SubRegIndex names to all ARM subregisters. This will be required by
...
TableGen shortly.
llvm-svn: 104754
2010-05-26 22:15:03 +00:00
996bc42a26
Stackrestore is not a load.
...
llvm-svn: 104752
2010-05-26 22:00:10 +00:00
ddee3cb163
Add FIXME comment to remove this.
...
llvm-svn: 104749
2010-05-26 21:53:50 +00:00
c96c6db59d
Remove a TODO which isn't practical.
...
llvm-svn: 104748
2010-05-26 21:50:41 +00:00
b33dfbcba4
MC: Add TargetMachine support for setting the value of MCRelaxAll with
...
-filetype=obj.
llvm-svn: 104747
2010-05-26 21:48:55 +00:00
d1d7ed63ff
Add StringRef::compare_numeric and use it to sort TableGen register records.
...
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
llvm-svn: 104745
2010-05-26 21:47:28 +00:00
1249adf160
Implement checking of the tail keyword.
...
llvm-svn: 104744
2010-05-26 21:46:36 +00:00
acc32a5c19
There is no need to force an line number entry (using previous location) for a temp label at unknown location.
...
llvm-svn: 104740
2010-05-26 21:23:46 +00:00
27311269cb
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
...
usual suspects that could "return twice".
llvm-svn: 104737
2010-05-26 20:39:00 +00:00
b889fc987e
MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments.
...
llvm-svn: 104736
2010-05-26 20:37:03 +00:00
9d40ef162b
MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment.
...
llvm-svn: 104735
2010-05-26 20:37:00 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
...
ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
1b08572a66
Update debug info when live-in reg is copied into a vreg.
...
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
70e34983e8
Fix the x86 move to/from segment register instructions.
...
llvm-svn: 104731
2010-05-26 20:10:45 +00:00
0c3bfd3fb0
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
...
more than just the stack slot coloring algorithm.
llvm-svn: 104722
2010-05-26 19:46:12 +00:00
002d54ddc9
Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().
...
llvm-svn: 104720
2010-05-26 19:37:24 +00:00
52c2738324
Eliminate the use of PriorityQueue and just use a std::vector,
...
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
llvm-svn: 104718
2010-05-26 18:52:00 +00:00
1e5d0b0456
Delete an unused function.
...
llvm-svn: 104716
2010-05-26 18:34:12 +00:00
7c8bd0fc98
MC: Change RelaxInstruction to only take the input and output instructions.
...
llvm-svn: 104713
2010-05-26 18:15:06 +00:00
338674a323
Fix a typo in a comment that Gabor noticed.
...
llvm-svn: 104711
2010-05-26 18:03:53 +00:00
388ff9b1a2
MC: Eliminate an unnecessary copy.
...
llvm-svn: 104709
2010-05-26 17:50:16 +00:00
a19838e107
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
...
before encoding.
llvm-svn: 104707
2010-05-26 17:45:29 +00:00
95fcc96752
Remove dead code.
...
llvm-svn: 104706
2010-05-26 17:42:50 +00:00
5a5e0bc3b5
Do not construct location list backword!
...
llvm-svn: 104705
2010-05-26 17:29:32 +00:00
7de379467e
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
2010-05-26 17:27:12 +00:00
b34440a6a8
MC: Eliminate MCAsmFixup, replace with MCFixup.
...
llvm-svn: 104699
2010-05-26 15:18:56 +00:00
353a91ff76
MC: Use accessors for access to MCAsmFixup.
...
llvm-svn: 104697
2010-05-26 15:18:31 +00:00
3627af5da4
MC: Change MCInst::dump_pretty to not include a trailing newline.
...
llvm-svn: 104696
2010-05-26 15:18:13 +00:00
6877119ef3
Kill unneeded SExt.
...
llvm-svn: 104692
2010-05-26 09:45:04 +00:00
730a977e02
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
...
llvm-svn: 104691
2010-05-26 08:10:02 +00:00
870e5759e7
MC: Eliminate MCFragment vtable, which was unnecessary.
...
llvm-svn: 104689
2010-05-26 06:50:57 +00:00
c4376b9b1b
Coding style change (Adding 1 missing space.)
...
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
0568ca0ddc
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
llvm-svn: 104667
2010-05-26 03:21:39 +00:00
e805ea9e39
Temporarily revert r104655 as it's breaking the bots.
...
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
50eec620f4
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
...
This reverts commit 104654.
llvm-svn: 104660
2010-05-26 01:21:14 +00:00
7c00576a62
Change push_all to a non-virtual function and implement it in the
...
base class, since all the implementations are the same.
llvm-svn: 104659
2010-05-26 01:10:55 +00:00
3701b3928e
Trim #include.
...
llvm-svn: 104657
2010-05-26 00:55:59 +00:00
c5222d6c38
Dale and Evan suggested putting the "check for setjmp" much earlier in the
...
machine code generation. That's a good idea, so I made it so.
llvm-svn: 104655
2010-05-26 00:32:40 +00:00
0b0274524c
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
2010-05-26 00:28:19 +00:00
b6e0bc9457
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
llvm-svn: 104653
2010-05-26 00:25:05 +00:00
e22abfa823
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
llvm-svn: 104652
2010-05-26 00:02:28 +00:00
e7b64dcc1e
Start adding mach-o tls reloc support.
...
llvm-svn: 104651
2010-05-26 00:02:12 +00:00
66c939a2ca
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
...
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
9fc11706e3
First cut at supporting .debug_loc section.
...
This is used to track variable information.
llvm-svn: 104649
2010-05-25 23:40:22 +00:00
9439084cea
Properly promote operands when optimizing a single-character memcmp.
...
llvm-svn: 104648
2010-05-25 22:53:43 +00:00
388f638511
Constify function.
...
llvm-svn: 104646
2010-05-25 22:02:22 +00:00
ce3269b815
Do one map lookup instead of two.
...
llvm-svn: 104645
2010-05-25 21:59:42 +00:00
a4abd035ea
Fix a missing newline in debug output.
...
llvm-svn: 104644
2010-05-25 21:50:35 +00:00
f3925438e5
Move the verbose asm output up a bit so it can be used in the special cases
...
as well.
llvm-svn: 104642
2010-05-25 21:49:43 +00:00
b04ef0cfbc
Okay, bear with me here...
...
If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
llvm-svn: 104640
2010-05-25 21:44:26 +00:00
19a4b843cc
Add support for initialized global data for darwin tls. Update comments
...
and testcases accordingly.
llvm-svn: 104635
2010-05-25 21:28:50 +00:00
492d4f409a
Changed the encoding of X86 floating point stack operations where both operands
...
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
2010-05-25 20:52:34 +00:00
3311eb50d7
Separate unrelated cases that once shared a numeric value
...
llvm-svn: 104629
2010-05-25 19:49:40 +00:00
1ad0d5e25b
Print symbolic SubRegIndex names on machine operands.
...
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
673e7e0f37
Remove NumberHack entirely.
...
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
2010-05-25 19:49:33 +00:00
0e767d7364
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
...
llvm-svn: 104626
2010-05-25 19:49:32 +00:00
60fe2cdc4f
Fix another variant of PR 7191. Also add a testcase
...
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
llvm-svn: 104624
2010-05-25 18:47:23 +00:00
4a5b2c597b
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
...
llvm-svn: 104622
2010-05-25 18:40:53 +00:00
c798965e63
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
llvm-svn: 104621
2010-05-25 18:16:58 +00:00
ff384ad981
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
...
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
llvm-svn: 104619
2010-05-25 17:50:03 +00:00
f6562d35ac
Make sure aeskeygenassist uses an unsigned immediate field.
...
Fixes rdar://8017638
llvm-svn: 104617
2010-05-25 17:33:22 +00:00
3b59e0601e
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
...
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
llvm-svn: 104615
2010-05-25 17:21:04 +00:00
36caaf1c59
Use enums instead of literals for SystemZ subregisters
...
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
396c8802b2
Use enums instead of literals for X86 subregisters.
...
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
llvm-svn: 104611
2010-05-25 17:04:16 +00:00
a6714e8a43
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
2da5aa1b60
Add support to MOVimm32 using movt/movw for ARM JIT
...
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
26fdebcae9
Clean up indentation.
...
llvm-svn: 104580
2010-05-25 03:36:52 +00:00
adff18518a
Disable invalid coalescer assertion.
...
llvm-svn: 104574
2010-05-25 00:15:18 +00:00
70affbd988
Use enums instead of literals in the ARM backend.
...
llvm-svn: 104573
2010-05-25 00:15:15 +00:00
0b7488e8d5
Print out the name of the function during SSC.
...
llvm-svn: 104572
2010-05-24 23:16:04 +00:00
fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
...
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
1181a19318
Lose the dummies
...
llvm-svn: 104564
2010-05-24 21:47:01 +00:00
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
...
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
1b79babdec
Avoid adding duplicate function live-in's.
...
llvm-svn: 104560
2010-05-24 21:33:37 +00:00
79b6a0f140
Fix an mmx movd encoding.
...
llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
...
llvm-svn: 104549
2010-05-24 20:32:23 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
51b37e0bd8
Do not emit line number entries for unknown debug values.
...
This fixes recent regression in store.exp from gdb testsuite.
llvm-svn: 104524
2010-05-24 18:26:49 +00:00
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
...
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
...
never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
8a57aeca2a
Use SubRegIndex in SystemZ.
...
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
5d56769fb6
SubRegIndex'ize Mips
...
llvm-svn: 104514
2010-05-24 17:42:58 +00:00
fd6f16fab9
SubRegIndex'ize MSP430
...
llvm-svn: 104513
2010-05-24 17:42:55 +00:00
Dan Gohman