3f8126e6fa
[AVX-512] Remove an AddedComplexity that was prioritizing basic vzmovl patterns over more complex ones that produce better code.
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llvm-svn: 278593
2016-08-13 05:43:20 +00:00
600685d510
[AVX-512] Add patterns to support VZEXT_MOVL from 512-bit vectors with 64-bit and 32-bit elements.
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Fixes PR28961.
llvm-svn: 278592
2016-08-13 05:33:12 +00:00
643734c565
[X86][AVX512] Added avx512 VPSLLDQ/VPSRLDQ instruction comments
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llvm-svn: 272319
2016-06-09 22:03:15 +00:00
0ab9d3026a
[X86][AVX512] Added support for lowering 512-bit vector shuffles to bit/byte shifts
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512-bit VPSLLDQ/VPSRLDQ can only be used for avx512bw targets so lowerVectorShuffleAsShift had to be adjusted to include the subtarget
llvm-svn: 272300
2016-06-09 20:13:58 +00:00
7a2993093e
[X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions.
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llvm-svn: 272249
2016-06-09 07:06:38 +00:00
143446d5c1
[AVX512] Add PALIGNR shuffle lowering for v32i16 and v16i32.
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llvm-svn: 271870
2016-06-06 05:39:10 +00:00
8eeda57a40
[AVX512] Add support for lowering PALIGNR for v64i8.
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Could do this for other types to, but this is what's needed to replace the instrinsic with native IR in clang.
llvm-svn: 271828
2016-06-05 06:29:12 +00:00
5a315d4613
[AVX512] Split command lines and regenerate a test to prepare for a future commit.
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llvm-svn: 271827
2016-06-05 06:29:08 +00:00
38f78a2b92
AVX-512: Fixed a bug in shuffle for v64i8 type
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Operation SCALAR_TO_VECTOR for v64i8 and v32i16 should be lowered if BW feature is "on".
Differential Revision: http://reviews.llvm.org/D17994
llvm-svn: 263097
2016-03-10 08:32:09 +00:00
Craig Topper