bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
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llvm-svn: 89440
2009-11-20 02:10:27 +00:00
b18525937c
More consistent thumb1 asm printing.
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llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
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llvm-svn: 89326
2009-11-19 06:32:27 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
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llvm-svn: 89143
2009-11-17 21:24:11 +00:00
a2873f4d59
Forgot to commit test fixes
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llvm-svn: 89138
2009-11-17 20:38:36 +00:00
0ad7efbace
Convert to FileCheck
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llvm-svn: 89007
2009-11-17 00:20:26 +00:00
4781c3caf8
Convert to FileCheck
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llvm-svn: 89002
2009-11-17 00:03:38 +00:00
805d195649
Cleanup. Missed removing these when converting. Oops.
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llvm-svn: 89001
2009-11-17 00:00:33 +00:00
1deb0b9f53
Convert to FileCheck
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llvm-svn: 88991
2009-11-16 23:19:29 +00:00
9b32e22ad1
Convert to FileCheck
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llvm-svn: 88947
2009-11-16 20:04:15 +00:00
980d94164d
Convert to FileCheck
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llvm-svn: 88942
2009-11-16 19:46:46 +00:00
c670bdc311
tbb opt off by default
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llvm-svn: 88921
2009-11-16 17:24:45 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
f16a3b7a9f
remove xfail
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llvm-svn: 88817
2009-11-14 21:57:35 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
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llvm-svn: 88734
2009-11-14 01:50:00 +00:00
1025a4998b
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
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llvm-svn: 86997
2009-11-12 17:19:09 +00:00
5218176bc6
Fix typo in run line.
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llvm-svn: 86984
2009-11-12 12:35:27 +00:00
5d85a46f76
RegScavenger::enterBasicBlock should always reset register state.
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llvm-svn: 86972
2009-11-12 07:49:10 +00:00
85a9f430e9
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
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cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
llvm-svn: 86969
2009-11-12 07:35:05 +00:00
64b5d0f468
Add support for tail duplication to BranchFolding, and extend
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tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
llvm-svn: 86871
2009-11-11 19:48:59 +00:00
47e3bcf180
Update test
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llvm-svn: 86614
2009-11-09 22:59:01 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
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except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
db42ca663b
Fix a broken test.
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llvm-svn: 86298
2009-11-06 23:06:42 +00:00
8f4e3d99c9
Fix test.
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llvm-svn: 85986
2009-11-04 00:42:33 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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llvm-svn: 85871
2009-11-03 05:52:54 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
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llvm-svn: 85848
2009-11-03 00:37:36 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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llvm-svn: 85787
2009-11-02 04:44:55 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
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llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50bc004b67
Fix tests.
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llvm-svn: 85723
2009-11-01 18:13:29 +00:00
6f29ad9170
Use cbz and cbnz instructions.
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llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
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them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
403202aef1
Consolidate test files
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llvm-svn: 85696
2009-10-31 22:20:56 +00:00
c79fb530d4
Change to use FileCheck
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llvm-svn: 85695
2009-10-31 22:16:14 +00:00
69f364babc
Make tests more explicit about which instructions are expected.
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llvm-svn: 85694
2009-10-31 22:14:17 +00:00
259c37cc55
Grammar tweak to comments
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llvm-svn: 85693
2009-10-31 22:12:44 +00:00
2c3e618a06
Update test to be more explicit about what instruction sequences are expected for each operation.
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llvm-svn: 85691
2009-10-31 22:10:38 +00:00
6ef6fe1c31
Force triple; darwin's ASM syntax differs from linux's.
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llvm-svn: 85676
2009-10-31 19:54:06 +00:00
7e06083a3a
Add missing colons for FileCheck.
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llvm-svn: 85674
2009-10-31 19:22:24 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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llvm-svn: 85643
2009-10-31 03:39:36 +00:00
3d43b38f0f
Fix Thumb2 failures by converting them to FileCheck.
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llvm-svn: 85210
2009-10-27 06:31:02 +00:00
69140ec4fa
Add a couple of ARM cross-rc coalescing tests.
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llvm-svn: 85051
2009-10-25 08:01:41 +00:00
b9f3520660
Update tests.
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llvm-svn: 85050
2009-10-25 07:53:48 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
682a2d154a
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
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llvm-svn: 84727
2009-10-21 01:44:44 +00:00
baf6dd26ea
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
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llvm-svn: 84658
2009-10-20 19:54:44 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
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llvm-svn: 84212
2009-10-15 22:25:32 +00:00
4ad726b4be
Fix tests.
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llvm-svn: 83241
2009-10-02 06:53:57 +00:00
1cc6dd97da
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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llvm-svn: 83218
2009-10-01 22:19:57 +00:00
3ea1ba7739
Forgot this test earlier.
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llvm-svn: 83143
2009-09-30 08:41:27 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
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llvm-svn: 82893
2009-09-27 09:46:04 +00:00
ccde96e96b
"Update" tests for -disable-if-conversion removal. I think branch.ll should just
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be removed, but I XFAIL'd it for now.
llvm-svn: 82847
2009-09-26 05:29:36 +00:00
a080159a7c
Convert more tests to avoid llvm-as.
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llvm-svn: 81545
2009-09-11 18:36:27 +00:00
cf61d68eaf
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
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llvm-svn: 81318
2009-09-09 06:05:16 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
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llvm-svn: 81293
2009-09-09 00:09:15 +00:00
f87421f088
update various tests for signedness changes in .s file.
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llvm-svn: 81289
2009-09-08 23:51:06 +00:00
9ef94277f1
adjust for signedness change. I'd appreciate it if an ARM flavored person
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could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)
llvm-svn: 81288
2009-09-08 23:44:53 +00:00
6837964819
merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes.
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llvm-svn: 81285
2009-09-08 23:41:06 +00:00
3d2fce01aa
Run branch folding if if-converter make some transformations.
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llvm-svn: 80994
2009-09-04 07:47:40 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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llvm-svn: 80615
2009-08-31 20:14:07 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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llvm-svn: 80191
2009-08-27 01:23:50 +00:00
9054d25808
Fix a typo. Somehow I thought this had passed before, but I guess not.
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llvm-svn: 79937
2009-08-24 21:17:17 +00:00
5fe1d38607
Convert slow test to use FileCheck.
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llvm-svn: 79935
2009-08-24 20:33:47 +00:00
a41fa35992
Make tail merging handle blocks with repeated predecessors correctly, and
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remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.
Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.
test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.
Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.
llvm-svn: 79338
2009-08-18 15:18:18 +00:00
dd406177de
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
d7e1a79eea
Fix tests.
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llvm-svn: 79086
2009-08-15 08:23:11 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
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llvm-svn: 79039
2009-08-14 20:48:13 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
608d92c943
Remove an Darwin assembler workaround.
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llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
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llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
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llvm-svn: 78659
2009-08-11 09:37:40 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
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llvm-svn: 78622
2009-08-10 23:56:04 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
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llvm-svn: 78594
2009-08-10 20:25:59 +00:00
ac51533b8a
Simplify RegScavenger::forward a bit more.
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Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
2009-08-08 13:18:47 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
b1aeeed03e
Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
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llvm-svn: 78376
2009-08-07 07:14:14 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
ea2b82b8fc
Disable stack coloring with register for now. It's not able to set kill markers.
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llvm-svn: 78179
2009-08-05 07:26:17 +00:00
a2ce665f60
Another nasty coalescer bug (is there another kind):
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After coalescing reg1027's def and kill are both at the same point:
%reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
bb5:
60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
Do not remove the kill marker on t2LDRi12.
llvm-svn: 78178
2009-08-05 07:05:41 +00:00
1f7b549c79
One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.
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llvm-svn: 78145
2009-08-05 02:25:11 +00:00
6376367356
One more place where subreg lowering forgot to transfer undefness.
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llvm-svn: 78144
2009-08-05 01:57:22 +00:00
cdb125ce66
If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
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llvm-svn: 78141
2009-08-05 01:29:24 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
28c2d9809d
Fix test.
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llvm-svn: 78113
2009-08-04 22:22:58 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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llvm-svn: 78104
2009-08-04 21:12:13 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
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llvm-svn: 78086
2009-08-04 18:46:17 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
093e124256
Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
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llvm-svn: 77967
2009-08-03 08:41:59 +00:00
8b9deebba3
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
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llvm-svn: 77939
2009-08-03 02:38:06 +00:00
Evan Cheng