Commit Graph

142929 Commits

Author SHA1 Message Date
Dean Michael Berris 4ebc79bb05 [XRay] Use regular expression for finding symbols
Un-break the test in Windows.

Follow-up on D24376.

llvm-svn: 291538
2017-01-10 04:32:34 +00:00
Craig Topper 2ed461e5c4 [X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails.
Fixes PR31593.

llvm-svn: 291535
2017-01-10 04:12:24 +00:00
Craig Topper d915d6ba57 [DAGCombiner] Remove code for optimizing select (xor Cond, 0), X, Y -> select Cond, X, Y. Just let combine on the xor itself take care of it.
llvm-svn: 291534
2017-01-10 04:12:19 +00:00
Dean Michael Berris f45ecd6eb7 [XRay] Fixup includes for modules build
Remove unnecessary system header include.

Follow-up to D24376.

llvm-svn: 291533
2017-01-10 03:21:54 +00:00
Xin Tong 02b1397ac3 Fix a typo and also test a new machine for commit. NFC.
llvm-svn: 291532
2017-01-10 03:13:52 +00:00
Dean Michael Berris d2791c604d [XRay] Don't include <unistd.h> unnecessarily
Follow-up to D24376.

llvm-svn: 291531
2017-01-10 02:51:13 +00:00
Serge Pavlov 0668cd2c95 [StructurizeCfg] Update dominator info.
In some cases StructurizeCfg updates root node, but dominator info
remains unchanges, it causes crash when expensive checks are enabled.
To cope with this problem a new method was added to DominatorTreeBase
that allows adding new root nodes, it is called in StructurizeCfg to
put dominator tree in sync.

This change fixes PR27488.

Differential Revision: https://reviews.llvm.org/D28114

llvm-svn: 291530
2017-01-10 02:50:47 +00:00
Dean Michael Berris f8f909f848 [XRay] Implement `llvm-xray convert` -- trace file conversion
This is the second part of a multi-part change to define additional
subcommands to the `llvm-xray` tool.

This change defines a conversion subcommand to take XRay log files, and
turns them from one format to another (binary or YAML). This currently
only supports the first version of the log file format, defined in the
compiler-rt runtime.

Depends on D21987.

Reviewers: dblaikie, echristo

Subscribers: mehdi_amini, dberris, beanz, llvm-commits

Differential Revision: https://reviews.llvm.org/D24376

llvm-svn: 291529
2017-01-10 02:38:11 +00:00
Evandro Menezes 063259d4d1 [CodeGen] Implement the SUnit::print() method
This method seems to have had a troubled life.  This patch proposes that it
replaces the recently added helper function dumpSUIdentifier.  This way, the
method can be used in other files using the SUnit class.

Differential revision: https://reviews.llvm.org/D28488

llvm-svn: 291520
2017-01-10 01:08:01 +00:00
Reid Kleckner 4ed2942004 Try once again to fix the MSVC build of AlignedCharArrayUnion
It was complaining about ambiguity between llvm::detail and
llvm::support::detail:
  error C2872: 'detail': ambiguous symbol
  note: could be 'llvm::detail'
  note: or       'llvm::support::detail'

Standardize on llvm::support::detail to hide these symbols further.

llvm-svn: 291519
2017-01-10 01:05:33 +00:00
Mehdi Amini c92b612636 [ThinLTO] Hash more part of the config to build cache entries
This has been fixed in the "new" LTO API used by Gold/LLD, this is
fixing the same issue in the libLTO API used by ld64 (amongst other)

llvm-svn: 291518
2017-01-10 00:55:47 +00:00
Xin Tong 12c8cb3745 Add an assert for hasLoopInvariantOperands
Summary: Add an assert for hasLoopInvariantOperands

Reviewers: danielcdh, sanjoy

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D28501

llvm-svn: 291516
2017-01-10 00:39:49 +00:00
Reid Kleckner ff27fec26b Revert the attempt to optimize the constexpr functions. MSVC does not handle this yet
llvm-svn: 291515
2017-01-10 00:29:05 +00:00
Reid Kleckner 9aa2b31a02 Fix MSVC build of AlignedCharArrayUnion
Use constexpr recursion for alignof like we do for sizeof. Seems to work
with Clang and MSVC. Also, don't recurse twice to avoid slowdowns in
compilers that don't memoize constexpr results (Clang).

llvm-svn: 291514
2017-01-10 00:26:56 +00:00
Sean Callanan 4d9c5c2280 Lift the 10-type limit for AlignedCharArrayUnion
This patch uses C++11 parameter packs and constexpr functions
to allow AlignedCharArrayUnion to hold an arbitrary number of
types.

Differential Revision: https://reviews.llvm.org/D28429

llvm-svn: 291503
2017-01-09 23:23:25 +00:00
James Y Knight 5b30b67cd1 Commit a test for match-full-lines.
I unfortunately neglected to add it in r260540, but it has been
sitting in my working dir ever since. D'oh.

Modified to work with r290069, which made the CHECK patterns
themselves whitespace-sensitive as well, and remove the test added
then, as this tests both strict and non-strict modes.

llvm-svn: 291499
2017-01-09 23:11:25 +00:00
Dan Gohman 6055fbae62 [WebAssembly] Add return type annotations in fast isel.
llvm-svn: 291498
2017-01-09 23:09:38 +00:00
Rui Ueyama e9d17545bc TarWriter: Fix a bug in Ustar header.
If we split a filename into `Name` and `Prefix`, `Prefix` is at most
145 bytes. We had a bug that didn't split a path correctly. This bug
was pointed out by Rafael in the post commit review.

This patch adds a unit test for TarWriter to verify the fix.

llvm-svn: 291494
2017-01-09 22:55:00 +00:00
Eugene Zelenko c9f1f6b8ec [NVPTX] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 291490
2017-01-09 22:16:51 +00:00
Simon Pilgrim fa32894730 [X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests
llvm-svn: 291488
2017-01-09 22:13:51 +00:00
Easwaran Raman e08b139d7d Refactor inline threshold update code.
Functional change: Previously, if a callee is cold, we used ColdThreshold if it minimizes the existing threshold. This was irrespective of whether we were optimizing for minsize (-Oz) or not. But -Oz uses very low threshold to begin with and the inlining with -Oz is expected to be tuned for lowering code size, so there is no good reason to set an even lower threshold for cold callees. We now lower the threshold for cold callees only when -Oz is not used. For default values of -inlinethreshold and -inlinecold-threshold, this change has no effect and this simplifies the code.

NFC changes: Group all threshold updates that are guarded by !Caller->optForMinSize() and within that group threshold updates that require profile summary info.

Differential revision: https://reviews.llvm.org/D28369

llvm-svn: 291487
2017-01-09 21:56:26 +00:00
Davide Italiano 472684eaf5 [SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).
Differential Revision:  https://reviews.llvm.org/D28479

llvm-svn: 291486
2017-01-09 21:55:23 +00:00
Rafael Espindola d4b24eda73 Support outputting to /dev/null.
When writing to a non regular file we cannot rename to it. Since we
have to write, we may as well create a temporary file to avoid trying
to create an unique file in /dev when trying to write to /dev/null.

llvm-svn: 291485
2017-01-09 21:52:35 +00:00
Matthias Braun ba7d95d425 PeepholeOptimizer: Do not replace SubregToReg(bitcast like)
While we can usually replace bitcast like instructions
(MachineInstr::isBitcast()) with a COPY this is not legal if any of the
users uses SUBREG_TO_REG to assert the upper bits of the result are
zero.

Differential Revision: https://reviews.llvm.org/D28474

llvm-svn: 291483
2017-01-09 21:38:17 +00:00
Matthias Braun c612891cc5 Drive by typo fix
llvm-svn: 291482
2017-01-09 21:38:14 +00:00
Matthias Braun a37430844c MachineInstr: Print name for subreg index in SUBREG_TO_REG
SUBREG_TO_REG takes a subregister index as 3rd operand, print the name
instead of a number. We already do the same for INSERT_SUBREG and
REG_SEQUENCE.

llvm-svn: 291481
2017-01-09 21:38:10 +00:00
Rui Ueyama a84ab073d9 TarWriter: Set "00" to Ustar version field.
Most (maybe all?) tar commands can handle tar archives with blank
version fields, but POSIX requires "00" to be set to the field, so
doing it is good for compliance.

llvm-svn: 291479
2017-01-09 21:20:42 +00:00
Michael Kuperstein 1559e8863e Revert r291092 because it introduces a crash.
See PR31589 for details.

llvm-svn: 291478
2017-01-09 21:04:46 +00:00
Vyacheslav Klochkov d497d36083 X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.
Differential Revision: https://reviews.llvm.org/D28087

llvm-svn: 291473
2017-01-09 20:26:17 +00:00
Sanjay Patel 8f4910e26a [InstCombine] add test to show missed fold using llvm.assume; NFC
llvm-svn: 291472
2017-01-09 20:18:30 +00:00
Chris Bieneman e62e684fdd Revert "[ObjectYAML] Support for DWARF line tables"
This reverts commit r291470 due to failing bots:

http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio

llvm-svn: 291471
2017-01-09 20:04:55 +00:00
Chris Bieneman 0396f99184 [ObjectYAML] Support for DWARF line tables
This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.

llvm-svn: 291470
2017-01-09 20:01:37 +00:00
Sanjay Patel eaa143c98c [InstCombine] regenerate checks; NFC
llvm-svn: 291469
2017-01-09 19:43:26 +00:00
Sanjay Patel baac743254 [ValueTracking] regenerate checks; NFC
llvm-svn: 291468
2017-01-09 19:31:20 +00:00
Daniel Berlin 101db5f7bc Fix function regex in update_tests so it can handle {}'s in function args
llvm-svn: 291467
2017-01-09 19:24:19 +00:00
Sanjay Patel 87495eb8ef [InstCombine] regenerate checks; NFC
llvm-svn: 291464
2017-01-09 19:18:46 +00:00
Sanjay Patel ced8fdd42a [InstCombine] remove unnecessary attribute comments from test files; NFC
llvm-svn: 291463
2017-01-09 19:13:38 +00:00
Matthew Simpson cf796478e9 [LV] Fix-up external IV users after updating dominator tree
This patch delays the fix-up step for external induction variable users until
after the dominator tree has been properly updated. This should fix PR30742.
The SCEVExpander in InductionDescriptor::transform can generate code in the
wrong location if the dominator tree is not up-to-date. We should work towards
keeping the dominator tree up-to-date throughout the transformation.

Reference: https://llvm.org/bugs/show_bug.cgi?id=30742
Differential Revision: https://reviews.llvm.org/D28168

llvm-svn: 291462
2017-01-09 19:05:29 +00:00
Matt Arsenault 6dca542b4a AMDGPU: Add Assert[SZ]Ext during argument load creation
For i16 zeroext arguments when i16 was a legal type, the
known bits information from the truncate was lost. Insert
a zeroext so the known bits optimizations work with the 32-bit
loads.

Fixes code quality regressions vs. SI in min.ll test.

llvm-svn: 291461
2017-01-09 18:52:39 +00:00
Matt Arsenault 5f45e7890a Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")
llvm-svn: 291460
2017-01-09 18:44:11 +00:00
Xin Tong c13a8e84d1 Intrinsic::Bitreverse is safe to speculate
Summary: Intrinsic::Bitreverse is safe to speculate

Reviewers: hfinkel, mkuper, arsenm, jmolloy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28471

llvm-svn: 291456
2017-01-09 17:57:08 +00:00
Sumanth Gundapaneni 0ac1ce70ba In the below scenario, we must be able to skip the a DBG_VALUE instruction and
remove the dead store.

%vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4)
DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0 
S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF]

In reality, this kind of stores are eliminated before Stack Slot Coloring pass,
possibly in instruction lowering

Differential Revision: https://reviews.llvm.org/D26616

llvm-svn: 291455
2017-01-09 17:45:02 +00:00
Simon Pilgrim 0f23b2ba1a [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets.

Cost model updates to follow.

llvm-svn: 291451
2017-01-09 17:20:03 +00:00
Sanjay Patel 940c06188e fix comment typos; NFC
llvm-svn: 291447
2017-01-09 16:27:56 +00:00
Simon Pilgrim d990cd371b [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw).

Cost model updates to follow.

llvm-svn: 291445
2017-01-09 15:15:45 +00:00
Simon Pilgrim f8538572ab [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests
llvm-svn: 291444
2017-01-09 14:36:09 +00:00
Mohammed Agabaria e0e7cdf36c [IR] Adding const_value_op_iterator for IR/User.h
const value op iterator is missing from User.h class.

Differential Revision: https://reviews.llvm.org/D28464

llvm-svn: 291443
2017-01-09 14:00:57 +00:00
Amaury Sechet 7d6285fb1c Some formatting in TargetMachineC. NFC
llvm-svn: 291442
2017-01-09 13:54:51 +00:00
Bjorn Pettersson b14afd452d [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.
Summary:
Originally

 i64 = umax t8, Constant:i64<4>

was expanded into

 i32,i32 = umax Constant:i32<0>, Constant:i32<0>
 i32,i32 = umax t7, Constant:i32<4>

Now instead the two produced umax:es return i32 instead of i32, i32.

Thanks to Jan Vesely for help with the test case.

Patch by mikael.holmen at ericsson.com

Reviewers: bogner, jvesely, tstellarAMD, arsenm

Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D28135

llvm-svn: 291441
2017-01-09 12:03:50 +00:00
Eugene Leviant 74f27dc91b RuntimeDyldELF: add missing test cases for AArch64
llvm-svn: 291438
2017-01-09 11:47:33 +00:00