Commit Graph

47872 Commits

Author SHA1 Message Date
Chris Lattner 6bc5c89093 Stop accepting and ignoring attributes in function types. Attributes are applied
to functions and call/invokes, not to types.

llvm-svn: 133266
2011-06-17 17:37:13 +00:00
Jakub Staszak 2ce8399a2d Allow empty Weights vector.
llvm-svn: 133265
2011-06-17 17:30:10 +00:00
Roman Divacky d041962c20 Fix a few places where 32bit instructions/registerset were used on PPC64.
llvm-svn: 133260
2011-06-17 15:21:10 +00:00
Rafael Espindola e0304d1df9 Two fixes relating to debug value:
* We should change the generated code because of a debug use.
* Avoid creating debug uses of undef, as they become a kill.
Test to follow.

llvm-svn: 133255
2011-06-17 13:59:43 +00:00
Jay Foad afdfed3d47 Fix typo in comment.
llvm-svn: 133254
2011-06-17 13:36:06 +00:00
Justin Holewinski 3604d9a421 PTX: Adjust rounding modes
* rounding modes for fp add, mul, sub now use .rn
* float -> int rounding correctly uses .rzi not .rni
* 32bit fdiv for sm13 uses div.rn (instead of div.approx)
* 32bit fdiv for sm10 now uses div (instead of div.approx)

Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit.

All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend.

Patch by Dan Bailey

llvm-svn: 133253
2011-06-17 12:12:42 +00:00
Nick Lewycky e11f467dda When promoting an alloca to registers discard any lifetime intrinsics.
llvm-svn: 133251
2011-06-17 10:09:00 +00:00
Lang Hames 934625efc1 Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to PBQP allocation. Patch by Arnaud Allard de Grandmaison.
llvm-svn: 133249
2011-06-17 07:09:01 +00:00
Chris Lattner 5756c16cdf make the asmparser reject function and type redefinitions. 'Merging' hasn't been
needed since llvm-gcc 3.4 days.

llvm-svn: 133248
2011-06-17 07:06:44 +00:00
Chris Lattner 59345c8b65 remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue.
llvm-svn: 133247
2011-06-17 06:57:15 +00:00
Chris Lattner 33de427cd6 remove parser support for the obsolete "multiple return values" syntax, which
was replaced with return of a "first class aggregate".

llvm-svn: 133245
2011-06-17 06:49:41 +00:00
Chris Lattner 4649a73cc3 stop accepting begin/end around function bodies in the .ll parser, this isn't pascal anymore.
llvm-svn: 133244
2011-06-17 06:42:57 +00:00
Chris Lattner def1949c00 Remove support for using "foo" as symbols instead of %"foo". This is ancient
syntax and has been long obsolete.  As usual, updating the tests is the nasty
part of this.

llvm-svn: 133242
2011-06-17 06:36:20 +00:00
Rafael Espindola 79a4b7e55c Enable early duplication of small blocks. There are still improvements to
be made, but this is already a win.

llvm-svn: 133240
2011-06-17 05:54:50 +00:00
Jakob Stoklund Olesen 3982029f60 Allocate SystemZ callee-saved registers backwards: R13-R6
The reserved R14-R15 are always saved in the prolog, and using CSRs
starting from R13 allows them to be saved in one instruction.

Thanks to Anton for explaining this.

llvm-svn: 133233
2011-06-17 03:47:30 +00:00
Chris Lattner 7810372577 Remove old backwards compatibility support from the parser for autoupgrading
the old malloc/free instructions, and for 'sext' and 'zext' as function 
attributes (they are spelled signext/zeroext now), and support for result
value attributes being specified after a function.

Additionally, diagnose invalid attributes on functions with an error message
instead of an abort in the verifier.

llvm-svn: 133229
2011-06-17 03:16:47 +00:00
Cameron Zwarich 033026ffc0 Update an insertion point iterator after replacing a return instruction with a
tail call pseudoinstruction. This fixes <rdar://problem/9624333>.

llvm-svn: 133227
2011-06-17 02:16:43 +00:00
Jakob Stoklund Olesen 66773c3398 Explicitly invoke ArrayRef constructor to keep gcc happy.
Patch by Richard Smith!

llvm-svn: 133220
2011-06-17 00:18:25 +00:00
Jakob Stoklund Olesen 801f7ab321 Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

llvm-svn: 133216
2011-06-16 23:31:16 +00:00
Jakob Stoklund Olesen c826df9506 Don't use register classes larger than TLI->getRegClassFor(VT).
In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210
2011-06-16 22:50:38 +00:00
Jakob Stoklund Olesen 4f5f84c7e7 Teach antidependency breakers to use RegisterClassInfo.
No functional change was intended.

llvm-svn: 133202
2011-06-16 21:56:21 +00:00
Chris Lattner 9f7c0657d2 change Type.h to forward declare ArrayRef instead of #including it.
llvm-svn: 133197
2011-06-16 21:37:15 +00:00
Chris Lattner 99807bc8ce prune #includes.
llvm-svn: 133194
2011-06-16 21:27:52 +00:00
Chris Lattner 60a1f6b091 move the address space into the subclass data field, saving a word on PointerType.
This limits the # address spaces to 2^23, which should be good enough.

llvm-svn: 133192
2011-06-16 21:17:17 +00:00
Chris Lattner 4528229157 tidy up some comments, store the 'isvararg' bit for FunctionType in
the SubclassData field, saving a word.

llvm-svn: 133191
2011-06-16 21:08:21 +00:00
Chris Lattner be452708fc remove Type::getVAArgsPromotedType, which is dead, and tidy up a bit.
llvm-svn: 133190
2011-06-16 21:00:43 +00:00
Dan Gohman 00fa9634d5 Fix ARCOpt to insert releases on both successors of an invoke rather
than trying to insert them immediately after the invoke.

llvm-svn: 133188
2011-06-16 20:57:14 +00:00
Jakob Stoklund Olesen 08322b7dc3 Move PBQP off allocation_order_begin. No functional change intended.
I think PBQP could use RegisterClassInfo, but it didn't fit neatly with
the external interfaces that PBQP uses, so I'll leave that to Lang.

llvm-svn: 133186
2011-06-16 20:37:45 +00:00
Jakub Staszak 12a43bdde5 Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184
2011-06-16 20:22:37 +00:00
Owen Anderson 5fc8b77f83 Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178
2011-06-16 18:17:13 +00:00
Jakob Stoklund Olesen 89a7e5ad45 Switch linear scan to using RegisterClassInfo.
This avoids the manual filtering of reserved registers and removes the
dependency on allocation_order_begin().

Palliative care...

llvm-svn: 133177
2011-06-16 18:17:00 +00:00
Bruno Cardoso Lopes d66ab9ead1 Mark ldrexd/strexd w/ volatile memory by default
llvm-svn: 133175
2011-06-16 18:11:32 +00:00
Jakub Staszak feadd435c1 Test commit.
llvm-svn: 133174
2011-06-16 18:01:17 +00:00
Justin Holewinski 7f191b2a3b PTX: Finish new calling convention implementation
llvm-svn: 133172
2011-06-16 17:50:00 +00:00
Justin Holewinski 6b356c1f3f PTX: Rename register classes for readability and combine int and fp registers
llvm-svn: 133171
2011-06-16 17:49:58 +00:00
Jakob Stoklund Olesen 1f641d577e Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.

Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.

llvm-svn: 133170
2011-06-16 17:42:25 +00:00
Dan Gohman 8eb36ef497 Add a comment describing why transforming (shl x, 1) to (add x, x) is to be
considered safe enough in this context.

llvm-svn: 133159
2011-06-16 15:55:48 +00:00
Justin Holewinski 5ccf812b1d PTX: Fix whitespace errors
llvm-svn: 133158
2011-06-16 15:17:11 +00:00
Bruno Cardoso Lopes bbf2ab990f Add AVX suport for fpextend.
Original patch by Syoyo Fujita with more comments by me.

llvm-svn: 133153
2011-06-16 07:03:21 +00:00
Chad Rosier 2730162bee Revision r128665 added an optimization to make use of NEON multiplier
accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.

llvm-svn: 133127
2011-06-16 01:21:54 +00:00
Nick Lewycky 6d677cfdd8 Add a DAGCombine for (ext (binop (load x), cst)).
llvm-svn: 133124
2011-06-16 01:15:49 +00:00
Bruno Cardoso Lopes 5444a7b4cd Silence warnings in non assert builds. Patch by David Blaikie
llvm-svn: 133118
2011-06-16 00:40:02 +00:00
Anna Zaks 2c2aa9a9be Function::getNumBlockIDs() should be used instead of Function::size() to set the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix).
llvm-svn: 133113
2011-06-16 00:03:21 +00:00
Eli Friedman 8b098b0d57 Add a limit to the number of instructions memdep will scan in a single block. This prevents (at least in some cases) O(N^2) runtime in passes like DSE.
The limit in this patch is probably too high, but it is enough to stop DSE from going completely insane on a testcase I have (which has a single block with around 50,000 non-aliasing stores in it).

rdar://9471075

llvm-svn: 133111
2011-06-15 23:59:25 +00:00
John McCall d935e9c359 The ARC language-specific optimizer. Credit to Dan Gohman.
llvm-svn: 133108
2011-06-15 23:37:01 +00:00
Owen Anderson 96adc4a540 Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
llvm-svn: 133106
2011-06-15 23:35:18 +00:00
Jakob Stoklund Olesen 99f35eab45 Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105
2011-06-15 23:28:14 +00:00
Eli Friedman 19ace4c31a Simplify; no significant functionality change.
llvm-svn: 133086
2011-06-15 21:08:25 +00:00
Rafael Espindola ea7a02774d Fix cmake build.
llvm-svn: 133085
2011-06-15 21:03:04 +00:00
Rafael Espindola ab20567227 Handle jump tables. Test to follow soon.
llvm-svn: 133083
2011-06-15 21:00:28 +00:00
John McCall 4b7a8d68ae Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080
2011-06-15 20:36:13 +00:00
Eli Friedman a472b7d900 Remove unused code.
llvm-svn: 133078
2011-06-15 19:58:09 +00:00
Jim Grosbach c7e6b8fed5 Diagnostic for undefined assembler local symbols.
Re-apply 133010, with fixes for inline assembler.

Original commit message:
"When an assembler local symbol is used but not defined in a module, a
Darwin assembler wants to issue a diagnostic to that effect."

Added fix to only perform the check when finalizing, as otherwise we're not
done and undefined symbols may simply not have been encountered yet.

Passes "make check" and a self-host check on Darwin.

llvm-svn: 133071
2011-06-15 18:33:28 +00:00
Jakob Stoklund Olesen 5977109f14 Remove custom allocation orders in SystemZ.
Note that this actually changes code generation, and someone who
understands this target better should check the changes.

- R12Q is now allocatable. I think it was omitted from the allocation
  order by mistake since it isn't reserved. It as apparently used as a
  GOT pointer sometimes, and it should probably be reserved if that is
  the case.

- The GR64 registers are allocated in a different order now. The
  register allocator will automatically put the CSRs last. There were
  other changes to the order that may have been significant.

The test fix is because r0 and r1 swapped places in the allocation order.

llvm-svn: 133067
2011-06-15 18:02:56 +00:00
Evan Cheng 678b691aa3 Another revsh pattern. rdar://9609059
llvm-svn: 133064
2011-06-15 17:17:48 +00:00
Andrew Trick 3013b6ae4a Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched.

llvm-svn: 133063
2011-06-15 17:16:12 +00:00
Roman Divacky 6874b26d0f Make PPC64CompilationCallback compilable no non-darwin platforms.
Patch by Nathan Whitehorn!

llvm-svn: 133059
2011-06-15 15:29:47 +00:00
Nadav Rotem 13cb7736a7 getZeroExtendInReg needs to get a scalar type
llvm-svn: 133057
2011-06-15 14:37:18 +00:00
Nadav Rotem d2d9bdb2b0 Enable the simplification of truncating-store after fixing the usage of
GetDemandBits (which must operate on the vector element type).

Fix the a usage of getZeroExtendInReg which must also be done on scalar types.

llvm-svn: 133052
2011-06-15 11:19:12 +00:00
Owen Anderson 86fd3c0058 Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries.  Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time.  It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.

llvm-svn: 133051
2011-06-15 06:53:50 +00:00
Nick Lewycky 5bcbd73c38 Teach the .ll parser to handle named metadata with non-simple names.
Unfortunately we can't follow what the rest of the language does (wrapping it
in double-quotes) because that would cause an ambiguity with metadata strings,
so instead we escape any unusual characters with \xx escaping.

llvm-svn: 133050
2011-06-15 06:37:58 +00:00
Bob Wilson 4b12a11f30 A minor simplification: no functional change.
llvm-svn: 133047
2011-06-15 06:04:34 +00:00
Eli Friedman e8bbc10880 Stop using memdep for a check that didn't really make sense with memdep. In terms of specific issues, using memdep here checks irrelevant instructions and won't work properly once we start returning "unknown" more aggressively from memdep.
llvm-svn: 133035
2011-06-15 01:25:56 +00:00
Evan Cheng 6d02d9044b PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
the bits being cleared by the AND are not demanded by the BFI.

The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).

rdar://9609030

llvm-svn: 133034
2011-06-15 01:12:31 +00:00
Ted Kremenek b05f02e956 add option for literal formatting to APInt::toString()
toString() now takes an optional bool argument that,
depending on the radix, adds the appropriate prefix
to the integer's string representation that makes it into a
meaningful C literal, e.g.:

hexademical: '-f' becomes '-0xf'
octal: '77' becomes '077'
binary: '110' becomes '0b110'

Patch by nobled@dreamwidth.org!

llvm-svn: 133032
2011-06-15 00:51:55 +00:00
Eli Friedman 7d58bc7bc0 Add "unknown" results for memdep, which mean "I don't know whether a dependence for the given instruction exists in the given block". This cleans up all the existing hacks in memdep which represent this concept by returning clobber with various unrelated instructions.
llvm-svn: 133031
2011-06-15 00:47:34 +00:00
Tanya Lattner e9e6705cf9 Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add.
Includes a test case.

llvm-svn: 133027
2011-06-14 23:48:48 +00:00
Anna Zaks cd7f70e8b5 Anna's test commit (#2).
llvm-svn: 133023
2011-06-14 22:40:29 +00:00
Chad Rosier 818e116723 When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.

llvm-svn: 133022
2011-06-14 22:29:10 +00:00
Eli Friedman 164b1d753a PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg doesn't appear to be dead.
Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this?

llvm-svn: 133018
2011-06-14 22:16:20 +00:00
Anna Zaks d7f7fcd3cb Anna's test commit.
llvm-svn: 133017
2011-06-14 22:10:12 +00:00
Jim Grosbach ed1da49673 Revert 133010. Self-hosted buildbot unhappy.
Apparently llvm itself generates undefined assembler local labels, causing
self-hosting problems with this patch. Reverting until that's sorted out.

llvm-svn: 133013
2011-06-14 21:51:20 +00:00
Jim Grosbach 627e780902 Diagnostic for undefined assembler local symbols.
When an assembler local symbol is used but not defined in a module, a
Darwin assembler wants to issue a diagnostic to that effect.

rdar://9559714

llvm-svn: 133010
2011-06-14 21:13:25 +00:00
Eli Friedman 8a3264ad48 Revert r133004 ; it's breaking nightly tests.
llvm-svn: 133007
2011-06-14 19:30:33 +00:00
Rafael Espindola 5e85158321 Partial revert of 132882.
Dan noted that this would work on the case shown on the commit message. I think
the case that was failing was a bb ending with a redundant conditional jump:

...
jne foo

foo:
...

I was unable to find any such case in the tests or in a debug build of clang,
so I will revert this part of the patch and watch the bots.

llvm-svn: 133004
2011-06-14 18:12:31 +00:00
Evan Cheng 965ed2e790 Also recognize ARM v4t and v5e variants.
llvm-svn: 133002
2011-06-14 18:08:33 +00:00
Rafael Espindola 3aeaf9e4c1 Add 132986 back, but avoid non-determinism if a bb address gets reused.
llvm-svn: 132995
2011-06-14 15:31:54 +00:00
Rafael Espindola 06ba7a68de revert 132986 to see if the bots go green.
llvm-svn: 132988
2011-06-14 12:48:26 +00:00
Nadav Rotem 10193c830b Add a testcase for checking the integer-promotion of many different vector
types (with power of two types such as 8,16,32 .. 512).

Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding
only if the target of the conversion is an integer (when the type action is
scalarize).

Add handling to the legalization of vector load/store in cases where the saved
vector is integer-promoted.

llvm-svn: 132985
2011-06-14 08:11:52 +00:00
Nadav Rotem 571ae19af7 Disable trunc-store simplification on vectors.
llvm-svn: 132984
2011-06-14 07:18:26 +00:00
Cameron Zwarich b5f19d9f6f Be more obvious about what is being tested.
llvm-svn: 132982
2011-06-14 06:33:51 +00:00
Rafael Espindola 844485af13 Implement Jakob's suggestion on how to detect fall thought without calling
AnalyzeBranch.

llvm-svn: 132981
2011-06-14 06:08:32 +00:00
Bruno Cardoso Lopes dc9ff3a4b1 Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976
2011-06-14 04:58:37 +00:00
Rafael Espindola da24f2f8e1 Make the threshold used by branch folding softer. Before we would get a
sharp all or nothing transition when one extra predecessor was added. Now
we still test first ones for merging.

llvm-svn: 132974
2011-06-14 04:41:17 +00:00
Nick Lewycky 34a425b075 Fit banner in 80-col and adjust whitespace. No functionality changes.
llvm-svn: 132964
2011-06-14 03:23:52 +00:00
John McCall 5af845226c Use IRBuilder to make our intrinsic calls in the inliner so that we pick up
line info correctly.

llvm-svn: 132961
2011-06-14 02:51:53 +00:00
Evan Cheng cffdcae2fe Update BitcodeWriter to match recent Triple changes. rdar://9603399
llvm-svn: 132959
2011-06-14 01:51:33 +00:00
Nick Lewycky 9711b5c70b Use Value::stripPointerCasts instead of reinventing part of the wheel.
llvm-svn: 132954
2011-06-14 00:59:24 +00:00
Cameron Zwarich 922e4940bd Fix grammar.
llvm-svn: 132952
2011-06-13 23:39:23 +00:00
Jim Grosbach 7ef7ddd2df Clean up a few 80 column violations.
llvm-svn: 132946
2011-06-13 22:54:22 +00:00
Cameron Zwarich 3ecbd59c27 Rename MergeInType to MergeInTypeForLoadOrStore.
llvm-svn: 132940
2011-06-13 21:44:43 +00:00
Cameron Zwarich 8cb90ac456 Remove the HadAVector instance variable and replace it with a use of ScalarKind.
llvm-svn: 132939
2011-06-13 21:44:40 +00:00
Cameron Zwarich 1bfab48edb Remove a vacuous check.
llvm-svn: 132938
2011-06-13 21:44:38 +00:00
Cameron Zwarich 5e9a0be4b3 Have SRoA explicitly track the kind of scalar it is promoting. This is pretty
spartan right now, but I plan to encode more information in this enum to improve
the correctness and reliability of SRoA. At least this first pass makes it
possible to make VectorTy an actual VectorType.

llvm-svn: 132937
2011-06-13 21:44:35 +00:00
Cameron Zwarich 8deb615d64 Remove an argument that is always true.
llvm-svn: 132936
2011-06-13 21:44:31 +00:00
Jim Grosbach dca8531821 Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.

llvm-svn: 132934
2011-06-13 21:18:25 +00:00
Evan Cheng 871b71247b Aliased flag options should be directed to stdout, not stderr to be consistent. Patch by Julien Lerouge.
llvm-svn: 132931
2011-06-13 20:45:54 +00:00
Stuart Hastings 351a3f881f Avoid fusing bitcasts with dynamic allocas if the amount-to-allocate
might overflow.  Re-typing the alloca to a larger type (e.g. double)
hoists a shift into the alloca, potentially exposing overflow in the
expression.  rdar://problem/9265821

llvm-svn: 132926
2011-06-13 18:48:49 +00:00
Benjamin Kramer 558d09d87e Move class into an anonymous namespace.
llvm-svn: 132925
2011-06-13 18:38:56 +00:00
Nadav Rotem 573ee374a2 Fix a bug in FindMemType. When widening vector loads, use a wider memory type
only if the number of packed elements is a power of two.
Bug found in Duncan's testcase.

llvm-svn: 132923
2011-06-13 18:13:24 +00:00
Benjamin Kramer c970849ea0 InstCombine: Fold A-b == C --> b == A-C if A and C are constants.
The backend already knew this trick.

llvm-svn: 132915
2011-06-13 15:24:24 +00:00
Benjamin Kramer 975c29629f Revert r132910 and r132909 on behalf of Michael. They didn't build with clang.
llvm-svn: 132914
2011-06-13 12:56:51 +00:00
Michael J. Spencer aa41981dd8 Revert the last two commits in the series. r132911, r132912.
llvm-svn: 132913
2011-06-13 11:53:31 +00:00
Michael J. Spencer a7f9c49aab Make Binary the parent of ObjectFile and update children to new interface.
llvm-svn: 132911
2011-06-13 11:12:33 +00:00
Michael J. Spencer 7dc3c3de7e Add Binary class. This is a cleaner parent than ObjectFile.
llvm-svn: 132910
2011-06-13 11:12:12 +00:00
Michael J. Spencer 0901cec03e Add Object/Error.
llvm-svn: 132909
2011-06-13 11:11:59 +00:00
Michael J. Spencer 422504fba6 Fix spelling and sort CMakeLists.txt.
llvm-svn: 132908
2011-06-13 11:11:39 +00:00
Nick Lewycky f8e046b148 It's possible that an all-zero GEP may be used as the argument to lifetime
intrinsics. In fact, we'll optimize a bitcast to that when possible. Detect it
when looking for the lifetime intrinsics.

No test case, noticed by inspection.

llvm-svn: 132906
2011-06-13 07:52:46 +00:00
Jakob Stoklund Olesen fb03a92c33 Be less aggressive about hinting in RAFast.
In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.

The attached test case provides an example where the fast allocator
would spill a register when other registers are available.

llvm-svn: 132900
2011-06-13 03:26:46 +00:00
Jakob Stoklund Olesen f4f66f36c7 Include callee-saved registers in debug output.
llvm-svn: 132899
2011-06-13 03:26:42 +00:00
Rafael Espindola 51d2d7aabc Fix invalid uses of Twine. Hopefully this fixes the problem that Takumi is
having.

llvm-svn: 132898
2011-06-13 03:09:13 +00:00
Benjamin Kramer 91f914ce21 InstCombine: Shrink ((zext X) & C1) == C2 to fold away the cast if the "zext" and the "and" have one use.
llvm-svn: 132897
2011-06-12 22:48:00 +00:00
Benjamin Kramer 35159c114c Simplify code. No functionality changes, name changes aside.
llvm-svn: 132896
2011-06-12 22:47:53 +00:00
Nadav Rotem 504cf0cde2 Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd
types such as i33 were rounded to i32. Originated from Duncan's testcase.

llvm-svn: 132893
2011-06-12 14:56:55 +00:00
Nadav Rotem 083837e729 Improve the generated code by getCopyFromPartsVector for promoted integer types.
Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892
2011-06-12 14:49:38 +00:00
Rafael Espindola 2f3c2fe7c5 Really fix the fall-through logic.
Add a triple to the tests.

llvm-svn: 132885
2011-06-12 05:57:01 +00:00
Rafael Espindola 653a07206d Fix silly bug I introduce in the previous commit. Fixes debug builds.
llvm-svn: 132883
2011-06-12 05:26:32 +00:00
Rafael Espindola defd4b0875 AnalyzeBranch doesn't change which successors a bb has, just the order
we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882
2011-06-12 03:20:32 +00:00
Charles Davis 7ed40cbded Put FrameSetup flag on x86 instructions that set up the call frame. No
functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880
2011-06-12 01:45:54 +00:00
Chad Rosier 79044dbebf Revert r132871.
llvm-svn: 132872
2011-06-11 02:27:46 +00:00
Chad Rosier 5793b53027 Typo.
llvm-svn: 132871
2011-06-11 02:16:36 +00:00
Eli Friedman 1735b29196 Make sure to pass OpFlags into MachineInstrBuilder::addExternalSymbol; the
memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869
2011-06-11 01:55:07 +00:00
Andrew Trick 3d4e64b082 Branch profiling: floating-point avoidance.
Patch by: Jakub Staszak!

Introduces BranchProbability. Changes unsigned to uint32_t all over and
uint64_t only when overflow is expected.

llvm-svn: 132867
2011-06-11 01:05:22 +00:00
Eli Friedman cd2124a3f0 Add full x86 fast-isel support for memcpy and memset.
rdar://9431466

llvm-svn: 132864
2011-06-10 23:39:36 +00:00
Eric Christopher eb964516c3 80-col cleanups.
llvm-svn: 132863
2011-06-10 23:05:08 +00:00
Dan Gohman cc59548793 Initialize BasicAA's AliasCache to set it to use fewer buckets by
default, since it usually has very few elements. This speeds up
alias queries in many cases, because AliasCache.clear() doesn't
have to visit as many buckets.

llvm-svn: 132862
2011-06-10 22:30:30 +00:00
Rafael Espindola 0f62e4c428 Removed tabs. Also fixed my editor...
llvm-svn: 132857
2011-06-10 21:01:53 +00:00
Cameron Zwarich 890197859b Provide an ARMCCState subclass of CCState so that ARM clients will always set
CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856
2011-06-10 20:59:24 +00:00
Cameron Zwarich 8b58a83889 Rename the ParmContext enum values to make a bit more sense and add a small
comment on their meaning.

llvm-svn: 132854
2011-06-10 20:37:36 +00:00
Cameron Zwarich 6221139453 Remove tabs.
llvm-svn: 132853
2011-06-10 20:31:39 +00:00
Cameron Zwarich 86ceec1b42 Remove a pointless const_cast.
llvm-svn: 132852
2011-06-10 20:30:08 +00:00
Rafael Espindola 1ffadd7809 Remove duplicated test.
Thanks Bob Wilson for noticing it!

llvm-svn: 132851
2011-06-10 20:08:23 +00:00
Eli Friedman 87ef38784e PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.
llvm-svn: 132826
2011-06-10 01:13:01 +00:00
Chad Rosier b90a43d266 Ensure that EmitGlobalVariable is correctly differentiating between declarations
and definitions when emitting global variables.  This was causing global 
declarations to be emitted as if they were definitions.
Fixes <rdar://problem/9429892>.

llvm-svn: 132825
2011-06-10 00:53:15 +00:00
Rafael Espindola 9e97a895f3 Make the optional verification step more strict.
llvm-svn: 132822
2011-06-09 23:55:56 +00:00
Rafael Espindola c9e93a44be Avoid a gcc warning about multiline comments.
llvm-svn: 132821
2011-06-09 23:51:45 +00:00
Rafael Espindola c735f13368 On last fix to the early tail duplication.
With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.

llvm-svn: 132816
2011-06-09 23:22:56 +00:00
Eli Friedman 5abfd79900 Chris fixed this README a while back by changing how clang generates code for structs like the given struct.
llvm-svn: 132815
2011-06-09 23:02:19 +00:00
Rafael Espindola 81512fc1bb Also consider phi nodes when deciding if a register is live out.
llvm-svn: 132814
2011-06-09 22:53:47 +00:00
Cameron Zwarich 361548d4b4 A CCState was being created without setting whether it is in the Call or Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811
2011-06-09 22:30:07 +00:00
Eli Friedman 1877ac9937 Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809.
The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809
2011-06-09 22:14:44 +00:00
Rafael Espindola c90a32a4e6 AnalyzeBranch modifies the bb, but we don't want to modify a bb with
eh edges. Swap the order of the checks to avoid it.

llvm-svn: 132806
2011-06-09 21:43:25 +00:00
Rafael Espindola 887fc1bdeb A PHI in this basic block is a use in another basic block.
llvm-svn: 132805
2011-06-09 20:55:41 +00:00
John McCall 58fb52c6c7 When deleting a basic block, remove call edges only for non-intrinsics.
llvm-svn: 132803
2011-06-09 20:31:09 +00:00
Roman Divacky 4b5665a1f7 Fix emission of PPC64 assembler on non-darwin platforms by splitting
VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802
2011-06-09 20:25:38 +00:00
John McCall fc1ca36866 SplitCriticalEdge can sometimes split the edge from an invoke to a landing
pad, separating the exception and selector calls from the new lpad.  Teaching
it not to do that, or to properly adjust the CFG afterwards, is out of
scope because it would require the other edges to the landing pad to be split
as well (effectively).  Instead, just recover from the most likely cases
during inlining.  The best long-term solution is to change the exception
representation and commit to either requiring or not requiring the more
complex edge-splitting logic;  this is just a shorter-term hack.

llvm-svn: 132799
2011-06-09 20:06:24 +00:00
Rafael Espindola 73f93930e0 Refactor some checks into shouldTailDuplicate. Update comments.
No functionality change.

llvm-svn: 132798
2011-06-09 19:54:42 +00:00
John McCall 729c35b680 Teach the CallGraph to ignore calls to intrinsics.
llvm-svn: 132797
2011-06-09 19:46:27 +00:00
Eli Friedman 9008377c2d Revert 132789; it breaks tests. My mistake.
llvm-svn: 132795
2011-06-09 19:33:30 +00:00
Jason W Kim 7fbe7914af Remove an uneeded switch - Turns out reloc results are identical w/o the switch. (face+palm)
llvm-svn: 132790
2011-06-09 19:13:45 +00:00
Eli Friedman c095116710 Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.
llvm-svn: 132789
2011-06-09 18:55:00 +00:00
Jakob Stoklund Olesen 5750ca7089 Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
2011-06-09 16:56:59 +00:00
Eric Christopher f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
Eric Christopher cafa08cbf3 Recommit r132764 since it didn't cause the windows buildbot failures.
llvm-svn: 132776
2011-06-09 15:39:01 +00:00
Rafael Espindola b77c00fb60 Improve the handling of available_externally and llvm.global_ctors.
llvm-svn: 132775
2011-06-09 14:38:09 +00:00
Duncan Sands eeb50c8fd2 Enable printf() to iprintf() optimization for the TCE target.
Patch by Pekka Jaaskelainen. 

llvm-svn: 132774
2011-06-09 11:11:45 +00:00
Chris Lattner 889c40e2e1 add another sandybridge alias.
llvm-svn: 132772
2011-06-09 06:38:17 +00:00
Eric Christopher 76fd742d16 Temporarily revert 132764 to see if it fixes the Windows buildbot.
llvm-svn: 132771
2011-06-09 06:29:54 +00:00
Akira Hatanaka 0683a7212e Initial support for inline asm memory operand constraints.
llvm-svn: 132768
2011-06-09 03:31:05 +00:00
Cameron Zwarich c62894d440 Remove a vacuous condition.
llvm-svn: 132767
2011-06-09 01:52:44 +00:00
Cameron Zwarich 77a699a829 Fix PR10104 by adding a bounds check on a vector element access check. It was
assuming that all offsets are legal vector accesses, and thus trying to access
the float member of { <2 x float>, float } as the 3rd element of the first
member.

llvm-svn: 132766
2011-06-09 01:45:33 +00:00
Eric Christopher 11edab6a46 If the alignment of the byval argument is greater than the alignment
of the frame then increase the maximum alignment of the frame to
match.

Fixes PR6965

llvm-svn: 132764
2011-06-09 00:15:19 +00:00
Eric Christopher 0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Cameron Zwarich c3b1cc9aca Fix an assymmetry between ConvertScalar_ExtractValue and ConvertScalar_InsertValue. The
former was using the size of the entire alloca, whereas the latter was correctly using
the allocated size of the immediate type being converted (which may differ from the size
of the alloca). This fixes PR10082.

llvm-svn: 132759
2011-06-08 22:08:31 +00:00
Akira Hatanaka 4e9af454f7 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.

llvm-svn: 132758
2011-06-08 21:28:09 +00:00
Akira Hatanaka 195a1e2184 Reorganize code in MipsTargetLowering::LowerCall to improve readability.
llvm-svn: 132756
2011-06-08 17:39:33 +00:00
Andrew Trick 6ed0c63559 Remove a temporary test case probe in CheckForLiveRegDef.
llvm-svn: 132751
2011-06-08 15:19:49 +00:00
Rafael Espindola eabd18b931 Fix count.
llvm-svn: 132749
2011-06-08 14:23:19 +00:00
Rafael Espindola dfbf6de747 Count how many phis we are creating.
llvm-svn: 132748
2011-06-08 14:13:31 +00:00
Cameron Zwarich 2e252de512 Fix an issue where the two-address conversion pass incorrectly rewrites untied
operands to an early clobber register. This fixes <rdar://problem/9566076>.

llvm-svn: 132738
2011-06-07 23:54:00 +00:00
Rafael Espindola c85e0d81e4 Fix a silly error I introduce in r131951.
Fixes PR10095.

llvm-svn: 132735
2011-06-07 23:26:45 +00:00
Akira Hatanaka 41956cf6e3 Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
llvm-svn: 132726
2011-06-07 19:28:39 +00:00
Akira Hatanaka e99b08d6c3 Put back removed line.
llvm-svn: 132725
2011-06-07 19:03:14 +00:00
Akira Hatanaka 1550678765 Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
2011-06-07 18:58:42 +00:00
Akira Hatanaka dde4aac02b Use tabs to separate opcode and operand strings.
llvm-svn: 132718
2011-06-07 18:16:51 +00:00
Akira Hatanaka d8373a4680 Add comments for wrapper node patterns in MipsInstrInfo.td.
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
Roman Divacky 384ffa9a0e Make EmitIntValue() work properly on big-endian targets.
llvm-svn: 132715
2011-06-07 17:31:02 +00:00
Akira Hatanaka 08b7a779ef Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
2011-06-07 02:17:21 +00:00
Andrew Trick 0af2e47310 Fix a merge bug in preRAsched for handling physreg aliases.
I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.

llvm-svn: 132701
2011-06-07 00:38:12 +00:00
Andrew Trick 410172bf5e Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069

llvm-svn: 132699
2011-06-07 00:08:49 +00:00
Jakob Stoklund Olesen df476270eb Simplify local live range splitting's safeguard to fix PR10070.
When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.

This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.

llvm-svn: 132697
2011-06-06 23:55:20 +00:00
Stuart Hastings e0d3426e1a Followup to 132458, omit unnecessary stack copy when x87 input is a
load.  rdar://problem/6373334

llvm-svn: 132696
2011-06-06 23:15:58 +00:00
Jakob Stoklund Olesen 0cde8eb9e2 Get allocation orders from RegisterClassInfo when possible.
Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.

This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.

llvm-svn: 132690
2011-06-06 21:02:04 +00:00
Nadav Rotem c807fa5687 Add methods to support the integer-promotion of vector types. Methods to
legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.

llvm-svn: 132689
2011-06-06 20:55:56 +00:00
Stuart Hastings bee6fcc5aa Avoid FGETSIGN of 80-bit types. Fixes PR10085.
llvm-svn: 132681
2011-06-06 16:44:31 +00:00
Jakob Stoklund Olesen b7657d0225 Don't try to be clever, just preserve the target's allocation order.
The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.

When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.

We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.

llvm-svn: 132680
2011-06-06 16:36:30 +00:00
Eli Friedman bd375f1a3f PR10077: fix fast-isel of extractvalue of aggregate constants.
llvm-svn: 132676
2011-06-06 05:46:34 +00:00
Benjamin Kramer 440c3b7306 Use path API for path concatenation.
llvm-svn: 132668
2011-06-05 14:36:47 +00:00
Rafael Espindola 1134ab23df Basic support for macros with explicit arguments.
We still don't handle

* default values
* :req
* :vararg
* \()

llvm-svn: 132656
2011-06-05 02:43:45 +00:00
Rafael Espindola 940a0ee5ca Produce an undefined reference to _GLOBAL_OFFSET_TABLE_ if we have a
VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker
might need this, so I added a FIXME.

I could test this by duplicating test/MC/ELF/got.s, but it doesn't look
worthwhile.

llvm-svn: 132655
2011-06-05 01:20:06 +00:00
Nadav Rotem 06bd6d304e TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).
llvm-svn: 132649
2011-06-04 20:58:08 +00:00
Nadav Rotem 78d19bebe6 TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.
(only happens when using the -promote-elements option).

The correct legalization order is to first try to promote element. Next, we try
to widen vectors.

llvm-svn: 132648
2011-06-04 20:32:01 +00:00
Nick Lewycky 2176cdc98c Refactor parsing of variable names (ie., %foo and @foo) since they have the same
rules. Also refactor "read string until quote" into its own function. No
functionality change!

llvm-svn: 132645
2011-06-04 18:16:26 +00:00
Nick Lewycky 34fa1684e7 Add support for @GOTPTOFF in i386 mode.
llvm-svn: 132643
2011-06-04 17:38:07 +00:00
Bill Wendling 4f163dfed1 If the block that we're threading through is jumped to by an indirect branch,
then we don't want to set the destination in the indirect branch to the
destination. This is because the indirect branch needs its destinations to have
had their block addresses taken. This isn't so of the new critical edge that's
split during this process. If it turns out that the destination block has only
one predecessor, and that being a BB with an indirect branch, then it won't be
marked as 'used' and may be removed.
PR10072

llvm-svn: 132638
2011-06-04 09:42:04 +00:00
Dan Gohman adf80ae9e4 Reapply r131781, now that the GVN bug with partially-aliasing loads
is disabled.

llvm-svn: 132632
2011-06-04 06:50:18 +00:00
Dan Gohman a471751c24 Disable the main feature of 130180, the elimination of loads that are
redundant with partially-aliasing loads.

When computing what portion of a clobbering load value is needed,
it doesn't consider phi-translation which may have occurred
between the clobbing load and the redundant load.

llvm-svn: 132631
2011-06-04 06:48:50 +00:00
Dan Gohman 87fdceaf73 Revert r131781 again. Apparently there is more going on here.
llvm-svn: 132625
2011-06-04 05:11:22 +00:00
Nick Lewycky 75b2053863 Fold assert-only-used variable into the assert.
llvm-svn: 132620
2011-06-04 02:07:10 +00:00
Andrew Trick c73aa1ee81 Missing include of climits in the new BranchProbability pass.
llvm-svn: 132616
2011-06-04 01:30:52 +00:00
Andrew Trick 49371f3f33 New BranchProbabilityInfo analysis. Patch by Jakub Staszak!
BranchProbabilityInfo provides an interface for IR passes to query the
likelihood that control follows a CFG edge. This patch provides an
initial implementation of static branch predication that will populate
BranchProbabilityInfo for branches with no external profile
information using very simple heuristics. It currently isn't hooked up
to any external profile data, so static prediction does all the work.

llvm-svn: 132613
2011-06-04 01:16:30 +00:00
Dan Gohman 27b82f2f91 Reapply r131781 (revert r131809), now that some BasicAA shortcomings
it exposed are fixed.

llvm-svn: 132611
2011-06-04 00:46:31 +00:00
Dan Gohman fb02cec44e Fix BasicAA's recursion detection so that it doesn't pessimize
queries in the case of a DAG, where a query reaches a node
visited earlier, but it's not on a cycle. This avoids
MayAlias results in cases where BasicAA is expected to
return MustAlias or PartialAlias in order to protect TBAA.

llvm-svn: 132609
2011-06-04 00:31:50 +00:00
Stuart Hastings be605494ac Reapply 132424 with fixes. This fixes PR10068.
rdar://problem/5993888

llvm-svn: 132606
2011-06-03 23:53:54 +00:00
Jakob Stoklund Olesen e1c6d3acb4 Blackfin always uses a reserved call frame.
Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601
2011-06-03 22:45:18 +00:00
Eric Christopher 1e3e8933ed Another possible bug. Stopgap until we can autogenerate tables and
constraint lengths.

Part of rdar://9037836 and rdar://9119939

llvm-svn: 132598
2011-06-03 22:09:12 +00:00
Eric Christopher 761a5d4280 Fix an off by one error.
Part of rdar://9037836 and rdar://9119939

llvm-svn: 132590
2011-06-03 20:44:52 +00:00
Jakob Stoklund Olesen b8bf3c0f8b Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

llvm-svn: 132581
2011-06-03 20:34:53 +00:00
Jakob Stoklund Olesen 3460ae88b2 Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL)

Print out the computed allocation orders.

llvm-svn: 132580
2011-06-03 20:34:50 +00:00
Dan Gohman 4e7e7958d7 When merging MustAlias and PartialAlias, chose PartialAlias instead
of conservatively choosing MayAlias.

llvm-svn: 132579
2011-06-03 20:17:36 +00:00
Devang Patel 84bb33add9 Use IRBuilder, preserve line numbers.
llvm-svn: 132578
2011-06-03 19:46:19 +00:00
Eric Christopher 354b2a25f3 Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
2011-06-03 17:24:37 +00:00
Eric Christopher fbff0e4f26 Add a TODO about memory operands.
llvm-svn: 132559
2011-06-03 17:21:23 +00:00
Hans Wennborg 060b994a29 Test commit.
llvm-svn: 132558
2011-06-03 17:15:37 +00:00
Devang Patel 1d40024322 A typedef's context is not the same as type's context. It is the context of typedef decl itself. Use extra parameter to communicate this to DIBuilder.
llvm-svn: 132556
2011-06-03 17:04:51 +00:00
Chad Rosier 6a11b64c5e Revert name change from r132533. Lower case naming was intended per style guidelines.
llvm-svn: 132555
2011-06-03 17:02:19 +00:00
Roman Divacky a4a59aebd9 Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552
2011-06-03 15:47:49 +00:00
Zhongxing Xu 3e4abe5470 singed int causes signed extension, which contradicts the intention to pick up
integers with high 32 bits being zero.

llvm-svn: 132538
2011-06-03 08:29:51 +00:00
Nick Lewycky 611582401f Bail on unswitching a switch statement for a case with a critical edge. We name
which edge to split by pred/succ pair, which means that we can end up splitting
the wrong edge (by case value) in the switch statement entirely. Fixes PR10031!

llvm-svn: 132535
2011-06-03 06:27:15 +00:00
Chad Rosier 7ae2638d73 Whitespace and other cleanup. Functionallity unchanged.
llvm-svn: 132533
2011-06-03 05:09:12 +00:00
Eli Friedman 86585798af Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
rdar://9431157

llvm-svn: 132522
2011-06-03 01:13:19 +00:00
Andrew Trick 6bbaf133ba Basic PassManager diagnostics.
Added asserts whenever attempting to use a potentially
uninitialized pass. This helps people trying to develop a new pass and
people trying to understand the bug reports filed by the former people.

llvm-svn: 132520
2011-06-03 00:48:58 +00:00
Andrew Trick b3bddf0e72 whitespace
llvm-svn: 132519
2011-06-03 00:44:32 +00:00
Jakob Stoklund Olesen 4b0bb8396a Avoid calling TRI->getAllocatableSet in RAFast.
When compiling a program with lots of small functions like
483.xalancbmk, this makes RAFast 11% faster.

Add some comments to clarify the difference between unallocatable and
reserved registers. It's quite subtle.

The fast register allocator depends on EFLAGS' not being allocatable on
x86. That way it can completely avoid tracking liveness, and it won't
mind when there are multiple uses of a single def.

llvm-svn: 132514
2011-06-02 23:41:40 +00:00
Eric Christopher de9399bf76 Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939

llvm-svn: 132510
2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen 60cdf8e727 Flag unallocatable register classes instead of giving them empty
allocation orders.

llvm-svn: 132509
2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen 75703ca76f Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
2011-06-02 23:07:20 +00:00
Devang Patel 5127c5d9b2 Preserve line number information while converting Invoke into a Call.
llvm-svn: 132505
2011-06-02 22:46:58 +00:00
Jakob Stoklund Olesen e242ebea50 Just use a SmallVector.
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.

This should fix the test failures on darwin 9.

llvm-svn: 132500
2011-06-02 22:22:43 +00:00
Devang Patel 5ca0837397 Remove dead code.
llvm-svn: 132488
2011-06-02 21:31:00 +00:00
Devang Patel f02a376fbc Update DBG_VALUEs while breaking anti dependencies.
llvm-svn: 132487
2011-06-02 21:26:52 +00:00
Tanya Lattner f0759ef271 Fix encoding for VEXTdf.
llvm-svn: 132486
2011-06-02 21:25:24 +00:00
Eli Friedman 5da0ff41d7 PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid.
llvm-svn: 132485
2011-06-02 21:24:42 +00:00
Devang Patel e5feef0fe1 During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!

llvm-svn: 132483
2011-06-02 20:07:12 +00:00
Rafael Espindola aa318ae495 Revert 132424 to fix PR10068.
llvm-svn: 132479
2011-06-02 19:57:47 +00:00
Eric Christopher ca9b7bbaa1 Add a new parse hint for multi-letter constraints in inline asm.
Testcase will come when we use it.

Part of rdar://9119939

llvm-svn: 132476
2011-06-02 19:26:37 +00:00
Jakob Stoklund Olesen 50663b7485 Use RegisterClassInfo::getOrder in RAFast.
This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

llvm-svn: 132471
2011-06-02 18:35:30 +00:00
Jim Grosbach dac0238ed2 .cfi directive register parsing flexibility.
Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.

llvm-svn: 132466
2011-06-02 17:14:04 +00:00
Stuart Hastings 8d530ad22a Omit unnecessary stack copy when x87 input is a load.
rdar://problem/6373334

llvm-svn: 132458
2011-06-02 15:57:11 +00:00
Benjamin Kramer c8c4f7640a Start with a zeroed CSRNum map.
Found by valgrind.

llvm-svn: 132457
2011-06-02 12:07:44 +00:00
Jakob Stoklund Olesen 09e6667531 Initialize members to fix problem found by valgrind.
llvm-svn: 132456
2011-06-02 05:43:49 +00:00
Jakob Stoklund Olesen aff1060207 Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.

llvm-svn: 132455
2011-06-02 05:43:46 +00:00
Rafael Espindola d6860522b2 Don't hardcode the %reg format in the streamer.
llvm-svn: 132451
2011-06-02 02:34:55 +00:00
Jakob Stoklund Olesen c58894bc36 Add a RegisterClassInfo class that lazily caches information about
register classes.

It provides information for each register class that cannot be
determined statically, like:

- The number of allocatable registers in a class after filtering out the
  reserved and invalid registers.

- The preferred allocation order with registers that overlap callee-saved
  registers last.

- The last callee-saved register that overlaps a given physical register.

This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible.  The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.

Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.

llvm-svn: 132450
2011-06-02 02:19:35 +00:00
Akira Hatanaka 2446869410 Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
llvm-svn: 132448
2011-06-02 01:03:14 +00:00
Akira Hatanaka 6627752050 Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
llvm-svn: 132444
2011-06-02 00:24:44 +00:00
Eli Friedman b576b1675c When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though.
In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated).

The included testcase tests both this commit and r132434.

Part two of rdar://9429882.  (r132434 was mislabeled.)

llvm-svn: 132442
2011-06-02 00:08:52 +00:00
Eli Friedman 4b6eeb9ca2 In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 .
Testcase coming up soon.

llvm-svn: 132434
2011-06-01 23:16:53 +00:00
Devang Patel e7181b5fdb A DBG_VALUE that truncates a range does not start another dbg value range.
llvm-svn: 132433
2011-06-01 23:00:17 +00:00
Devang Patel 324f843107 Do not drop constant values when a variable's content is described using .debug_loc entries.
llvm-svn: 132427
2011-06-01 22:03:25 +00:00