2d497a0078
[NFC] Convert tabs to spaces.
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llvm-svn: 262411
2016-03-01 22:05:03 +00:00
6fdfa3dc32
[NFC] Referencing manual for reason why subregbit is checked
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llvm-svn: 259380
2016-02-01 18:15:39 +00:00
f57c1977c1
Reflect the MC/MCDisassembler split on the include/ level.
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No functional change, just moving code around.
llvm-svn: 258818
2016-01-26 16:44:37 +00:00
e5e035a3a8
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
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llvm-svn: 254843
2015-12-05 07:13:35 +00:00
d824f5f0d9
[Hexagon] Use array_lengthof and const correct and type correct the array and array size. NFC
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llvm-svn: 254384
2015-12-01 06:13:08 +00:00
6261e1b94d
Use array_lengthof instead of manually calculating it. NFC
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llvm-svn: 254383
2015-12-01 06:13:06 +00:00
3da000c07f
[Hexagon] Use ArrayRef to avoid needing to calculate an array size. Interestingly the original code may have had a bug because it was passing the byte size of a uint16_t array instead of the number of entries.
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llvm-svn: 254382
2015-12-01 06:13:04 +00:00
f0af6e5243
[Hexagon] Factoring bundle creation in to a utility function.
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llvm-svn: 253056
2015-11-13 17:42:46 +00:00
7cd0892729
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
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llvm-svn: 252443
2015-11-09 04:07:48 +00:00
160f73e36f
[Hexagon] Fixing mistaken case fallthrough.
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llvm-svn: 251867
2015-11-03 00:21:19 +00:00
7c9587136d
[Hexagon] Adding skeleton of HVX extension instructions.
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llvm-svn: 250600
2015-10-17 01:33:04 +00:00
f97999dc46
Explicitly clear the MI operand list when getInstruction() is called. Call MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler.
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Summary: Explicitly clear the MI operand list when getInstruction() is called.
Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11665
llvm-svn: 244557
2015-08-11 01:15:07 +00:00
f00654e31b
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
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Apparently, the style needs to be agreed upon first.
llvm-svn: 240390
2015-06-23 09:49:53 +00:00
70bc5f1398
Fixed/added namespace ending comments using clang-tidy. NFC
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The patch is generated using this command:
tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \
llvm/lib/
Thanks to Eugene Kosov for the original patch!
llvm-svn: 240137
2015-06-19 15:57:42 +00:00
1e9d1d768c
[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
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llvm-svn: 239477
2015-06-10 16:52:32 +00:00
be8c453d58
[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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llvm-svn: 239161
2015-06-05 16:00:11 +00:00
c40be85adc
Revert r239095 incorrect test tree.
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llvm-svn: 239102
2015-06-04 21:32:42 +00:00
fc52c11d80
[Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.
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llvm-svn: 239095
2015-06-04 21:16:16 +00:00
68d967d92e
[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
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llvm-svn: 238556
2015-05-29 14:44:13 +00:00
e9119e41ef
MC: Modernize MCOperand API naming. NFC.
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MCOperand::Create*() methods renamed to MCOperand::create*().
llvm-svn: 237275
2015-05-13 18:37:00 +00:00
1174fea31c
[Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo and eliminating HexagonMCInst class.
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llvm-svn: 229914
2015-02-19 21:10:50 +00:00
404d5b242d
[Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
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llvm-svn: 228708
2015-02-10 16:59:36 +00:00
d9903888d9
[cleanup] Re-sort all the #include lines in LLVM using
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utils/sort_includes.py.
I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.
llvm-svn: 225974
2015-01-14 11:23:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
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llvm-svn: 224869
2014-12-26 20:30:58 +00:00
f3db884efb
[Hexagon] Adding transfers to and from control registers.
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llvm-svn: 224599
2014-12-19 19:06:32 +00:00
383c36e3a8
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
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llvm-svn: 223494
2014-12-05 18:24:06 +00:00
5d6f03bd5a
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.
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llvm-svn: 223334
2014-12-04 03:41:21 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
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Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
7fc5b87480
Pass an ArrayRef to MCDisassembler::getInstruction.
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With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.
Even on X86 there is a maximum size an instruction can have. Given
that, it seems way simpler and more efficient to just pass an ArrayRef
to the disassembler instead of a MemoryObject and have it do a virtual
call every time it wants some extra bytes.
llvm-svn: 221751
2014-11-12 02:04:27 +00:00
4aa6bea7a2
Misc style fixes. NFC.
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This fixes a few cases of:
* Wrong variable name style.
* Lines longer than 80 columns.
* Repeated names in comments.
* clang-format of the above.
This make the next patch a lot easier to read.
llvm-svn: 221615
2014-11-10 18:11:10 +00:00
5241881bbc
[Hexagon] Reverting 220584 to address ASAN errors.
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llvm-svn: 221210
2014-11-04 00:14:36 +00:00
729be14435
Prune CRLF.
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llvm-svn: 220678
2014-10-27 12:37:26 +00:00
838307b31f
[Hexagon] Resubmission of 220427
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Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220584
2014-10-24 19:00:32 +00:00
504bbf91cd
Revert r220427, "[Hexagon] Adding encoding bits for add opcode."
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It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.
llvm-svn: 220478
2014-10-23 11:31:22 +00:00
73a51a1a68
[Hexagon] Adding encoding bits for add opcode.
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Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220427
2014-10-22 20:58:35 +00:00
db08566588
Fix VS2012 build; C++11 type aliases are not supported.
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llvm-svn: 220399
2014-10-22 17:47:49 +00:00
b424cb1e57
Ammending 220393 - Removing unused decoding tables.
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llvm-svn: 220397
2014-10-22 17:23:01 +00:00
9950d5c59a
Ammending 220393 - Removing unused functions.
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llvm-svn: 220396
2014-10-22 17:03:19 +00:00
88ebb9e2da
[Hexagon] Adding basic disassembler.
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Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc
llvm-svn: 220393
2014-10-22 16:49:14 +00:00
Colin LeMahieu