681561901d
Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.
...
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization. For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.
llvm-svn: 142370
2011-10-18 17:34:47 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
...
llvm-svn: 142365
2011-10-18 17:16:30 +00:00
dfa7fb8fe6
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
...
llvm-svn: 142363
2011-10-18 17:09:35 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
...
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
1fb5bb126e
PTX: Fix disabling of MAD instruction selection
...
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
d278d35b13
Fix a bunch of unused variable warnings when doing a release
...
build with gcc-4.6.
llvm-svn: 142350
2011-10-18 12:44:00 +00:00
2b7a1ff77f
Coding style cleanups. No functionality change.
...
llvm-svn: 142341
2011-10-18 07:40:22 +00:00
49045ddb4c
Remove NaClMode
...
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
0ffe593a16
Add support for dynamic stack realignment when in thumb1 mode.
...
rdar://10288916
llvm-svn: 142337
2011-10-18 05:28:00 +00:00
1c192774b6
Commit test, capitalizing store... keep it simple.
...
llvm-svn: 142336
2011-10-18 04:44:36 +00:00
bab66789d5
Fix comment to refer to correct instruction
...
llvm-svn: 142334
2011-10-18 03:51:57 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
22d3adf6aa
Backing out patch. Will refactor to remove the AsmParser dependency on Target.
...
llvm-svn: 142323
2011-10-18 00:23:49 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
...
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
1d19f97ea5
Object: Add some types to SymbolRef::Type.
...
Some of these can be true at the same time and there are a lot to add,
so this should be turned into a bitfield. Some of the other accessors
should probably be folded into this.
llvm-svn: 142318
2011-10-17 23:55:06 +00:00
321731539e
Object: Add isSymbolAbsolute and getSymbolSection.
...
llvm-svn: 142317
2011-10-17 23:54:46 +00:00
017597540e
Object: Add isSymbolWeak.
...
llvm-svn: 142316
2011-10-17 23:54:22 +00:00
89a7a5ea1f
Object/COFF: Expose more data in the public API.
...
llvm-svn: 142315
2011-10-17 23:53:56 +00:00
4f91c2f2bd
Object: Implement casting for concrete classes.
...
llvm-svn: 142314
2011-10-17 23:53:37 +00:00
479a8fe75e
Minor style cleanup, no functionality change.
...
llvm-svn: 142307
2011-10-17 23:27:36 +00:00
6f1ccffc8e
Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies.
...
Thanks to Raphael Espindola for tracking down the CMake issues.
llvm-svn: 142306
2011-10-17 23:24:48 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
...
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
40f8f2ff24
Add support for a new extension to the .file directive:
...
.file filenumber "directory" "filename"
This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.
llvm-svn: 142300
2011-10-17 23:05:28 +00:00
b522550ce5
Add a few FIXME comments.
...
llvm-svn: 142299
2011-10-17 22:54:23 +00:00
a7107f992e
Teach the ARC optimizer about the !clang.arc.copy_on_escape metadata
...
tag on objc_retainBlock calls, which indicates that they may be
optimized away. rdar://10211286.
llvm-svn: 142298
2011-10-17 22:53:25 +00:00
f18eec158c
Tidy up.
...
llvm-svn: 142297
2011-10-17 22:41:42 +00:00
d2d0acdc04
142288 broke the build:
...
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)
Revert "Validate target data layout strings."
This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.
llvm-svn: 142296
2011-10-17 22:37:51 +00:00
7973e78800
Update DebugInfoFinder to match recent debug info encoding changes.
...
llvm-svn: 142295
2011-10-17 22:30:34 +00:00
aa9047d3f5
Now Igor, throw the switch...give my creation life!
...
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
llvm-svn: 142294
2011-10-17 22:26:23 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
0533a9508b
Validate target data layout strings.
...
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.
llvm-svn: 142288
2011-10-17 22:05:34 +00:00
d85bc104ef
When deleting a phi cycle after looking through copies, constrain the register
...
to match its final use.
With this change, all of test-suite compiles for Thumb2 with -verify-coalescing
enabled.
llvm-svn: 142287
2011-10-17 21:54:46 +00:00
0dfb159250
Use a SmallVector for intrinsic argument types.
...
llvm-svn: 142259
2011-10-17 21:33:26 +00:00
510fbcd440
Don't renumber the blocks here. This could cause problems later on if another
...
pass renumbers the blocks again.
llvm-svn: 142258
2011-10-17 21:32:56 +00:00
c68c8cb8d4
Add support for the Objective-C personality function to the instruction
...
combining of the landingpad instruction. The ObjC personality function acts
almost identically to the C++ personality function. In particular, it uses
"null" as a "catch-all" value.
llvm-svn: 142256
2011-10-17 21:20:24 +00:00
4373c21205
Pseudoinstructions should not be less constrained than the instruction they are
...
lowered to. This fixes a lot of verifier failures on the test suite.
llvm-svn: 142254
2011-10-17 21:20:13 +00:00
2ad0dee309
Tidy up organization.
...
llvm-svn: 142248
2011-10-17 21:00:11 +00:00
e664de33b1
Fix handling of the From parameter in StringRef::find.
...
Enable bounds checking to catch this kind of bug earlier.
llvm-svn: 142247
2011-10-17 20:49:40 +00:00
f7f223f69e
Add a call to EmitSjLjDispatchBlock.
...
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.
llvm-svn: 142245
2011-10-17 20:37:20 +00:00
2fbdcedbb1
Fix improperly formed assert() call.
...
llvm-svn: 142239
2011-10-17 20:22:59 +00:00
d39466760a
Object: Fix redundant name.
...
llvm-svn: 142238
2011-10-17 20:19:29 +00:00
aa563df759
Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289
...
llvm-svn: 142234
2011-10-17 19:50:12 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
652985764e
Revert change to function alignment b/c existing logic was fine
...
llvm-svn: 142224
2011-10-17 18:53:03 +00:00
34957911e7
Removed set, but unused variables.
...
Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
1736c14b85
Suppress partial retain+release elimination when there's a
...
possibility that it will span multiple CFG diamonds/triangles which
could have different controlling predicates. rdar://10282956
llvm-svn: 142222
2011-10-17 18:48:25 +00:00
63a4ea1859
Correct over-zealous removal of hack.
...
Some code want to check that *any* call within a function has the 'returns
twice' attribute, not just that the current function has one.
llvm-svn: 142221
2011-10-17 18:43:40 +00:00
975bfc9b45
Move class and instruction definitions for conditional moves to a seperate file.
...
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
3634f34659
Revert change made in r142205.
...
llvm-svn: 142217
2011-10-17 18:33:24 +00:00
33fe8f908c
Redefine count-leading 0s and 1s instructions.
...
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
8c446be204
Redefine mfhi/lo and mthi/lo instructions.
...
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
2a83a71c2a
Now that we have the ReturnsTwice function attribute, this method is
...
obsolete. Check the attribute instead.
<rdar://problem/8031714>
llvm-svn: 142212
2011-10-17 18:22:52 +00:00
0317b65367
Redefine multiply and divide instructions.
...
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
2736bbc09e
Add definition of a base class for logical shift/rotate instructions with two
...
source registers and redefine 32-bit and 64-bit instructions.
llvm-svn: 142210
2011-10-17 18:17:58 +00:00
afa70aa272
Remove >80-col line and unicode
...
llvm-svn: 142209
2011-10-17 18:10:08 +00:00
73081309c3
Add definition of a base class for logical shift/rotate immediate instructions
...
and have 32-bit and 64-bit instructions derive from it.
llvm-svn: 142207
2011-10-17 18:06:56 +00:00
c17257c4cb
Removed set, but unused variable.
...
Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142206
2011-10-17 18:01:59 +00:00
e3f27b79dc
Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
...
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
0050f59665
Fix CMake build.
...
llvm-svn: 142204
2011-10-17 17:50:39 +00:00
69a4565e65
It is safe to speculate load from GOT. This fixes performance regression caused by r141689.
...
Radar 10281206.
llvm-svn: 142202
2011-10-17 17:35:01 +00:00
76c8563239
svn mv Target/ARM/ARMGlobalMerge.cpp Transforms/Scalar/GlobalMerge.cpp
...
There is no reason to have simple IR level pass in lib/Target.
llvm-svn: 142200
2011-10-17 17:17:43 +00:00
0ade47acd0
Instructions for Book E PPC should be word aligned, set function alignment to reflect this
...
llvm-svn: 142194
2011-10-17 17:01:41 +00:00
e20793a4f1
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
...
llvm-svn: 142177
2011-10-17 05:33:10 +00:00
26d2780d07
Add comment explaining that the order of processing doesn't matter here.
...
llvm-svn: 142176
2011-10-17 05:25:09 +00:00
ad677b64db
Add PPC 440 scheduler and some associated tests (new files)
...
llvm-svn: 142171
2011-10-17 04:03:55 +00:00
6fa5697af0
Add PPC 440 scheduler and some associated tests
...
llvm-svn: 142170
2011-10-17 04:03:49 +00:00
3e8aa65bc2
Add a routine to swap branch instruction operands, and update any
...
profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.
Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.
Reviewed by Nick Lewycky!
llvm-svn: 142168
2011-10-17 01:11:57 +00:00
91f4faf877
Delete a dead member. Dunno if this was ever used, but the current code
...
directly manipulates the weights inside of the BranchProbabilityInfo
that is passed in.
llvm-svn: 142163
2011-10-16 22:27:54 +00:00
47e1db1e59
Add a proper LLVM banner to this file.
...
llvm-svn: 142162
2011-10-16 22:15:07 +00:00
486ff59a9f
Enable element promotion type legalization by deafault.
...
Changed tests which assumed that vectors are legalized by widening them.
llvm-svn: 142152
2011-10-16 20:31:33 +00:00
0a7e9ccf04
When looking for dependencies on the src pointer, scan the src pointer. Scanning
...
on the memcpy call will pull up other unrelated stuff. Fixes PR11142.
llvm-svn: 142150
2011-10-16 20:13:32 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
...
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
cc863b2bb6
Let printf do the formatting instead aligning strings ourselves.
...
While at it, merge some format strings.
llvm-svn: 142140
2011-10-16 16:30:34 +00:00
cb6b02a086
Twinify better.
...
llvm-svn: 142139
2011-10-16 15:46:29 +00:00
1930b003fe
Add AsmToken::getEndLoc and use it to add ranges to x86 asm register parsing.
...
<stdin>:1:12: error: register %rax is only available in 64-bit mode
incl %rax
^~~~
llvm-svn: 142137
2011-10-16 12:10:27 +00:00
d416bae5f2
X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.
...
<stdin>:1:4: error: invalid instruction mnemonic 'abc'
abc incl %edi
^~~
llvm-svn: 142135
2011-10-16 11:28:29 +00:00
47f5e30e78
PR11143: Save the old diagnostic handler and call it when munging diagnostics for #line directives.
...
This reenables proper inline asm diagnostics in clang
llvm-svn: 142132
2011-10-16 10:48:29 +00:00
bc25b6eb67
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
...
no pattern.
llvm-svn: 142130
2011-10-16 10:02:06 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
...
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
434b3bff44
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
...
These missing flags show up as errors when running -verify-coalescing on
test-suite.
llvm-svn: 142111
2011-10-16 06:38:10 +00:00
08ca5d35bd
Fix an obvious typo found when looking at nearby code.
...
llvm-svn: 142110
2011-10-16 06:38:06 +00:00
7284526aff
remove the dead 'ShowLine' argument from SMDiagnostic.
...
llvm-svn: 142108
2011-10-16 05:47:55 +00:00
03b80a4027
Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a
...
string, pass it around as an enum.
llvm-svn: 142107
2011-10-16 05:43:57 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
...
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
6c8879e3ab
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
...
llvm-svn: 142089
2011-10-16 00:21:51 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
45f0f87af5
The CELL backend cannot select patterns for vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.
...
llvm-svn: 142081
2011-10-15 20:05:17 +00:00
097106b77a
ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when promoting elements.
...
llvm-svn: 142080
2011-10-15 20:03:12 +00:00
5fb5e3b384
SmallVector -> array
...
llvm-svn: 142073
2011-10-15 13:28:31 +00:00
f537a6edd4
Don't replace all dominated uses if there is only one use, since that
...
use can't be dominated, saving one domtree lookup.
llvm-svn: 142066
2011-10-15 11:13:42 +00:00
4d681d7dc4
Add a bad char heuristic to StringRef::find.
...
Based on Horspool's simplified version of Boyer-Moore. We use a constant-sized table of
uint8_ts to keep cache thrashing low, needles bigger than 255 bytes are uncommon anyways.
The worst case is still O(n*m) but we do a lot better on the average case now.
llvm-svn: 142061
2011-10-15 10:08:31 +00:00
ebe13bc3f1
Move the legalization of vector loads and stores into LegalizeVectorOps. In some
...
cases we need the second type-legalization pass in order to support all cases.
llvm-svn: 142060
2011-10-15 07:41:10 +00:00
fd4ca0f4ac
Fix SCEVExpander assert during LSR: "argument of incompatible type".
...
Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.
llvm-svn: 142058
2011-10-15 06:19:55 +00:00
ea97a05fc5
Revert r142046, "Fix for llvm::sys::getHostTriple on Windows. Instead of relying on the triple"
...
It extremely breaks builds when optimization is enabled. Twine should not hold temporary objects.
By the way, I might feel sad if I saw "i786-" "i1586-" or "iF86-".
llvm-svn: 142055
2011-10-15 04:29:36 +00:00
559b8f2ae9
Fix for llvm::sys::getHostTriple on Windows. Instead of relying on the triple
...
from config.h, it discovers the triple based on the execution environment.
Patch by Aaron Ballman <aaron@aaronballman.com>
llvm-svn: 142046
2011-10-15 02:10:06 +00:00
7bc976a8ef
Windows/Memory.inc: Support the ability to allocate memory "near" another block of memory on Win32. It has fixed FIXME.
...
Thanks to Aaron Ballman!
llvm-svn: 142039
2011-10-15 01:58:16 +00:00
d50861c831
Fix indvars randomness by removing iteration over a map.
...
I rewrote the algorithm a while back so it doesn't require map lookup,
but neglected to change the data structure. This was caught by
llvm-gcc self host, not because there's anything special about
llvm-gcc, but because it is the only test for nondeterminism we
currently have. Unit tests don't work well for everything; we should
always try to have a nondeterminism stress test running.
Fixes PR11133: llvm-gcc self host .o mismatch after enable-iv-rewrite=false
llvm-svn: 142036
2011-10-15 01:38:14 +00:00
2730a0099a
Clear out the landing pad to call site map for each function.
...
This isn't put into the 'clear()' method because the information needs to stick
around (at least for a little bit) after the selection DAG is built.
llvm-svn: 142032
2011-10-15 01:00:26 +00:00
dd2b39d989
Mark tADDrSPi as having side effects again.
...
It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations. I am guessing that it got
moved across a stack pointer update.
Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.
llvm-svn: 142030
2011-10-15 00:57:13 +00:00
1809d6c0d5
Thumb1 does not support dynamic stack realignment.
...
rdar://10288916 is tracking this fix.
In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment. Lang's work now
prevents this from happening (LLVM commit r141599). Now that this really
shouldn't happen report a fatal error rather than silently generate bad code.
llvm-svn: 142028
2011-10-15 00:28:24 +00:00
9c1019c6c7
Mark registers as DEAD because they're really just clobbers.
...
llvm-svn: 142027
2011-10-15 00:27:44 +00:00
74d1da5a05
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
...
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
9e0cd1ee17
Make sure that the register is in the register class before adding it as a machine op.
...
llvm-svn: 142021
2011-10-14 23:55:44 +00:00
6f3f9a391e
Mark the invoke call instruction as implicitly defining the callee-saved registers.
...
The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.
llvm-svn: 142018
2011-10-14 23:34:37 +00:00
8a038652f2
constify array itself, don't iterate multiple times.
...
llvm-svn: 142013
2011-10-14 22:50:21 +00:00
ea166d44e7
Allow the source module to be materialized during the linking process.
...
llvm-svn: 142010
2011-10-14 22:17:46 +00:00
8b478360ef
Fix a non-firing assert. Change:
...
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
ab6158e2e3
ocaml bindings: add getopcode for constant and instruction, and int64_of_const.
...
llvm-svn: 141990
2011-10-14 20:37:49 +00:00
2e9affec15
bindings: tab and indentation fixes of my previous commits
...
llvm-svn: 141989
2011-10-14 20:37:42 +00:00
06fdaeb5d9
A few 80-col violations.
...
llvm-svn: 141988
2011-10-14 20:36:23 +00:00
4a49dee221
Disable code/data region symbols on ELF targets, where different mapping symbols are used for ARM/Thumb mode code. This should only be re-enabled once we have a solution to properly distinguish these.
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llvm-svn: 141984
2011-10-14 20:28:57 +00:00
450128a68c
Add an implementation of the CanLowerReturn function to the PPC backend
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llvm-svn: 141981
2011-10-14 19:51:36 +00:00
44419bfd54
Add f128 to datalayout string.
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llvm-svn: 141978
2011-10-14 19:14:50 +00:00
4903379088
initial test commit (remove whitespace)
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llvm-svn: 141972
2011-10-14 18:54:13 +00:00
06b6ccfe90
Update live-in lists when splitting critical edges.
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Fixes PR10814. Patch by Jan Sjödin!
llvm-svn: 141960
2011-10-14 17:25:46 +00:00
62b34a65f9
Revert r141932, r141936 and r141937.
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llvm-svn: 141959
2011-10-14 17:16:39 +00:00
400907cc41
Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4".
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Pointed out by George Russell.
llvm-svn: 141956
2011-10-14 15:53:48 +00:00
a447e0f38f
An instruction's operands aren't necessarily instructions or constants. They
...
could be arguments, for example.
No testcase because this is a bug-fix broken out of a larger optimization patch.
llvm-svn: 141951
2011-10-14 09:38:46 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
d9ea7c8c31
Definition of function getMipsRegisterNumbering.
...
Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141938
2011-10-14 03:04:24 +00:00
1742a2c093
Add definition of class MipsELFWriterInfo.
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Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141937
2011-10-14 02:55:47 +00:00
0fc7d7af5a
Add missing relocation types.
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Patch by Jack Carter and Reed Kotler at Mips.
llvm-svn: 141936
2011-10-14 02:47:50 +00:00
769fc971b4
Fixup enumerations.
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Patch by Jack Carter at Mips.
llvm-svn: 141934
2011-10-14 02:38:56 +00:00
4e2bfe0770
Add more Mips relocation types.
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Patch by Jack Carter at Mips.
llvm-svn: 141932
2011-10-14 02:17:30 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
...
TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
eafa9d50c2
V_SET0 has no side effects.
...
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.
This was part of the cause for PR11125, but the real bug was fixed
in r141923.
llvm-svn: 141924
2011-10-14 00:39:50 +00:00
7fb5632e73
Add value numbers when spilling dead defs.
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When spilling around an instruction with a dead def, remember to add a
value number for the def.
The missing value number wouldn't normally create problems since there
would be an incoming live range as well. However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.
The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.
This fixes part of PR11125.
llvm-svn: 141923
2011-10-14 00:34:31 +00:00
b46345d7c1
Avoid undefined behavior in negation in LSR. Patch by Ahmed Charles.
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Someone more familiar with LSR should double-check that the extra cast is actually doing the right thing in the overflow cases; I'm not completely confident that's that case.
llvm-svn: 141916
2011-10-13 23:48:33 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
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llvm-svn: 141914
2011-10-13 23:36:06 +00:00
a5abd03a8d
Simplify assertion, and avoid undefined shift. Based on patch by Ahmed Charles.
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llvm-svn: 141912
2011-10-13 23:27:48 +00:00
a7a90bfdab
Support/Windows: Add support modifying memory permissions on Windows. Patch by Aaron Ballman!
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llvm-svn: 141910
2011-10-13 23:16:01 +00:00
92734d6f46
Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles.
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llvm-svn: 141909
2011-10-13 23:13:35 +00:00
0084615924
Support/Windows: Add efficent RW mutex on Windows. Patch by Aaron Ballman!
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llvm-svn: 141907
2011-10-13 23:10:56 +00:00
53ba208c72
Avoid undefined behavior in signed integer negation. Patch by Ahmed Charles.
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llvm-svn: 141905
2011-10-13 22:49:56 +00:00
aa6ec39056
Simplify and avoid undefined shift. Based on patch by Ahmed Charles.
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llvm-svn: 141903
2011-10-13 22:40:23 +00:00
834bd602e6
ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
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llvm-svn: 141901
2011-10-13 22:30:10 +00:00
c1702c8f22
Enhance the memdep interface so that users can tell the difference between a dependency which cannot be calculated and a path reaching the entry point of the function. This patch introduces isNonFuncLocal, which replaces isUnknown in some cases.
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Patch by Xiaoyi Guo.
llvm-svn: 141896
2011-10-13 22:14:57 +00:00
870c1a3f15
Reapply r141870, SCEV expansion of post-inc.
...
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.
llvm-svn: 141895
2011-10-13 21:55:29 +00:00
76933f4c0b
Don't forget to reconstruct D after changing the scope that we're
...
looking at.
llvm-svn: 141892
2011-10-13 21:43:44 +00:00
9a28851e52
COFF: Implement sectionContainsSymbol for relocatable files only.
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llvm-svn: 141884
2011-10-13 20:36:54 +00:00
7e442569dc
Fix memory corruption I introduced a few checkins ago.
...
Self-review easily caught this obvious bug.
llvm-svn: 141880
2011-10-13 18:49:23 +00:00
44f76eafae
SETEND is not allowed in an IT block.
...
llvm-svn: 141874
2011-10-13 17:58:39 +00:00
41c253c35c
Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
...
llvm-svn: 141873
2011-10-13 17:58:24 +00:00
e15d6e14e3
LSR: Reuse the post-inc expansion of expressions.
...
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.
llvm-svn: 141870
2011-10-13 17:31:47 +00:00
1393ec29af
SCEV: Rewrite TrandformForPostIncUse to handle expression DAGs, not
...
just expression trees.
Partially fixes PR11090. Test case will be with the full fix.
llvm-svn: 141868
2011-10-13 17:21:09 +00:00
adfe72b33c
Slightly more useful tracing.
...
llvm-svn: 141867
2011-10-13 17:06:38 +00:00
3815de8d50
Mark 'branch indirect' instruction as an indirect branch.
...
Not having it confused assembly printing of jumptables.
llvm-svn: 141862
2011-10-13 11:40:03 +00:00
25f6d3e321
More closely follow libgcc, which has code after the `ret' instruction to
...
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.
llvm-svn: 141859
2011-10-13 08:24:19 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
22a690e3db
Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
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llvm-svn: 141856
2011-10-13 07:42:32 +00:00
86f7d3556c
Use an existing method.
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llvm-svn: 141855
2011-10-13 07:36:41 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141854
2011-10-13 07:09:14 +00:00
2fdcb1f045
Add 'implicit EFLAGS' to patterns for popcnt and lzcnt
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llvm-svn: 141853
2011-10-13 06:18:52 +00:00
d3043965b9
Elf_Word is not POD! Stop using it in a DenseMap.
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llvm-svn: 141851
2011-10-13 03:30:21 +00:00
594a545821
If MI is deleted then remove it from the set. If a new MI is created, it could
...
have the same address as the one we deleted, and we don't want that in the set
yet. Noticed by inspection.
llvm-svn: 141849
2011-10-13 02:16:18 +00:00
404feb9973
Tabs to spaces.
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llvm-svn: 141844
2011-10-13 01:09:50 +00:00
8488225984
Add missing braces to pacify GCC's -Wparentheses.
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llvm-svn: 141842
2011-10-13 00:54:59 +00:00
068dc91de9
Also inflate register classes around inline asm.
...
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
llvm-svn: 141836
2011-10-12 23:37:40 +00:00
35b362fab2
Add MachineInstr::getRegClassConstraint().
...
Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.
llvm-svn: 141835
2011-10-12 23:37:36 +00:00
1e73716eae
Extract a method for finding the inline asm flag operand.
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llvm-svn: 141834
2011-10-12 23:37:33 +00:00
24abd9d9b6
Encode register class constreaints in inline asm instructions.
...
The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.
Encode the original register class as part of the flag word for each
inline asm operand. This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.
llvm-svn: 141833
2011-10-12 23:37:29 +00:00
3e5409df77
We need to verify that the machine instruction we're using as a replacement for
...
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>
llvm-svn: 141830
2011-10-12 23:03:40 +00:00
979009ea61
Use a utility from MathExtras to clarify a check and avoid undefined behavior. Based on patch by Ahmed Charles.
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llvm-svn: 141829
2011-10-12 22:46:45 +00:00
000721f058
The VMAs stored in the symbol table of a MachO file are absolute addresses, not offsets from the section.
...
llvm-svn: 141828
2011-10-12 22:37:10 +00:00
34e1707fbb
Don't label a STAB debugging symbol as a function symbol.
...
llvm-svn: 141824
2011-10-12 22:23:12 +00:00
fb02ecde5e
sectionContainsSymbol needs to be based on VMA's rather than section indices to properly account for files with segment load commands that contain no sections.
...
llvm-svn: 141822
2011-10-12 22:21:32 +00:00
154a967c23
Fix a couple hash functions so that they do not depend on undefined shifts. Based on patch by Ahmed Charles.
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llvm-svn: 141820
2011-10-12 22:00:26 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
...
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
d433042388
Fix APFloat::getSmallestNormalized so the shift doesn't depend on undefined behavior. Patch from Ahmed Charles.
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llvm-svn: 141818
2011-10-12 21:56:19 +00:00
c53220134a
Fix APFloat::getLargest so that it actually returns the correct value. Found by accident while reviewing a patch to nearby code.
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llvm-svn: 141816
2011-10-12 21:51:36 +00:00
f903c154c7
Section indices in MachO symbol tables begin at 1, not 0.
...
llvm-svn: 141815
2011-10-12 21:43:24 +00:00
e7c0c499b8
Finish supporting cpp #file/line comments in assembler for error messages. So
...
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
llvm-svn: 141814
2011-10-12 21:38:39 +00:00
b35afcaa56
Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions.
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llvm-svn: 141813
2011-10-12 21:33:49 +00:00
2dffcebf77
To find the exiting VN of a LiveInterval from a block, use the previous slot
...
rather than the previous index. If a block has a single instruction, the
previous index may be in a different basic block.
I have no clue how this used to work on all of test-suite, because now this
failure is seen quite often when trying to compile code with -strong-phi-elim.
This fixes PR10252.
llvm-svn: 141812
2011-10-12 21:24:54 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
f895efaa45
Hoist vector.size() computation out of the loop. No functionality change.
...
llvm-svn: 141807
2011-10-12 20:20:48 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
...
llvm-svn: 141794
2011-10-12 18:11:24 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
...
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
d74c0e7c14
80 columns.
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llvm-svn: 141781
2011-10-12 16:36:01 +00:00
6966411f45
Tidy up. Formatting.
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llvm-svn: 141780
2011-10-12 16:34:37 +00:00
de239d2647
Fix a thinko that Nick noticed. The previous code actually worked as
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intended, but only by accident.
llvm-svn: 141779
2011-10-12 15:56:56 +00:00
9bfcf77638
lib/Object/ELFObjectFile.cpp: Fix undefined behavior for MC/ELF/many-section.s not to fail (on msvc).
...
DenseMap::lookup(k) would return "default constructor value" when k was not met. It would be useless when value type were POD.
llvm-svn: 141774
2011-10-12 10:28:55 +00:00
918cea2c27
Expand the check for a landing pad so that it looks at the basic block's
...
containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.
llvm-svn: 141767
2011-10-12 02:58:01 +00:00
35163e21dc
Use an existing function.
...
llvm-svn: 141763
2011-10-12 01:24:51 +00:00
3261c0fa6e
Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
...
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
c57febff4a
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
...
Remove unused classes.
llvm-svn: 141757
2011-10-12 00:56:06 +00:00
c585de670f
Add missing space.
...
llvm-svn: 141750
2011-10-12 00:14:31 +00:00
064c1c0e77
Fix indent in comment.
...
llvm-svn: 141749
2011-10-12 00:14:12 +00:00
af1389546e
Fix r141744.
...
1. The speculation check may not have been performed if the BB hasn't had a load
LICM candidate.
2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the
instruction even if it's in high register pressure situation.
llvm-svn: 141747
2011-10-12 00:09:14 +00:00
39c31a77b8
Fix -widen-vmovs liveness issues.
...
When widening a copy, we are reading a larger register that may not be
live. Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.
We now widen:
%S6<def> = COPY %S4<kill>, %D3<imp-def>
into:
%D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>
This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.
Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.
llvm-svn: 141746
2011-10-12 00:06:23 +00:00
f192ca0761
Refine r141689 with a tri-state variable.
...
Also teach MachineLICM to avoid "speculation" when register pressure is high.
llvm-svn: 141744
2011-10-11 23:48:44 +00:00
0f4ecf7548
Change name of class to ArithOverflowR.
...
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
8f0d549c4c
Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
...
instructions with two register operands derive from it.
llvm-svn: 141742
2011-10-11 23:38:52 +00:00
8d4f74a6b1
Fix comment.
...
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
6647b83087
Add a new wrapper node for a DILexicalBlock that encapsulates it and a
...
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.
This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.
Part of rdar://10246360
llvm-svn: 141729
2011-10-11 22:59:11 +00:00
57d1692750
Formatting.
...
llvm-svn: 141728
2011-10-11 22:59:04 +00:00
cbce39c8b9
Spacing.
...
llvm-svn: 141727
2011-10-11 22:58:58 +00:00
579ff6c39c
N.B. This is with the new EH scheme:
...
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.
I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.
llvm-svn: 141726
2011-10-11 22:42:31 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
1a761dcfbd
Fix PR11106 by correcting a typo that has been in the code for over a year. This
...
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.
llvm-svn: 141713
2011-10-11 21:26:40 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
037fc9311a
Clean up a few references to System/. We still have docs/SystemLibrary.html
...
lying around...
llvm-svn: 141703
2011-10-11 20:02:52 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
453d401a51
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141689
2011-10-11 18:09:58 +00:00
27c579dba4
Expose MachOObjectFile externally, like we do for COFF. First step in reducing the amount of special-purpose code needed for llvm-objdump.
...
llvm-svn: 141684
2011-10-11 17:32:27 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
...
llvm-svn: 141682
2011-10-11 17:29:55 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
...
llvm-svn: 141671
2011-10-11 15:59:20 +00:00
3283793c9a
Add support for legalization of vector SHL/SRA/SRL instructions
...
llvm-svn: 141667
2011-10-11 14:36:35 +00:00
e8ae98a8d9
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
...
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
llvm-svn: 141666
2011-10-11 12:55:35 +00:00
68591286bc
Fix a iterator out of bounds error, that triggers rarely.
...
llvm-svn: 141665
2011-10-11 12:55:18 +00:00
198fe81571
Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32)
...
llvm-svn: 141661
2011-10-11 11:25:16 +00:00
b521b6037b
Cleanup the trunc-store legalization code and add asserts.
...
llvm-svn: 141659
2011-10-11 10:04:25 +00:00
63bc541196
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
...
llvm-svn: 141656
2011-10-11 07:13:09 +00:00
0fbca75c17
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
...
llvm-svn: 141654
2011-10-11 07:01:37 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
d7515ccc47
Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
...
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.
llvm-svn: 141646
2011-10-11 06:10:30 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
29e7b315ac
Also create a shndx even if there are no symbols. This lets us test
...
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.
llvm-svn: 141641
2011-10-11 03:54:50 +00:00
43f01cae95
Reapply r141605 with fixes for appropriate handling of reserved section numbers
...
in st_shndx fields.
llvm-svn: 141639
2011-10-11 03:18:58 +00:00
7adc4370e0
Add support for .symtab_shnidx. Unfortunately, doing this required breaking a
...
layer of abstraction around SymbolRef where you can read its private
SymbolPimpl member.
llvm-svn: 141636
2011-10-11 02:57:48 +00:00
ecbe22bb8d
Add experimental -enable-lsr-phielim option.
...
I'm not sure we will need it in the long run, but the option is
currently useful for checking if the output of LSR is "clean".
llvm-svn: 141634
2011-10-11 02:30:45 +00:00
f9201c572e
Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
...
IVs.
Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.
llvm-svn: 141633
2011-10-11 02:28:51 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
da7c0f8f7d
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
...
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
llvm-svn: 141619
2011-10-11 00:59:06 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
f22f46bf25
Fixed natural stack alignment for Linux x86-32. Thanks Eli.
...
llvm-svn: 141616
2011-10-11 00:51:36 +00:00
fa55bc27cb
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
...
llvm-svn: 141615
2011-10-11 00:44:20 +00:00
35a90c4baf
Revert r141605 as it broke tests for llvm-nm.
...
llvm-svn: 141614
2011-10-11 00:38:56 +00:00
e6ced5b3d5
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
...
llvm-svn: 141613
2011-10-11 00:37:28 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
cbb9140806
Make it possible to use the linker without destroying the source module. This is so the source module can be linked to multiple other destination modules. For all that used LinkModules() before, they will continue to destroy the source module as before.
...
This line, and those below, will be ignored--
M include/llvm/Linker.h
M tools/bugpoint/Miscompilation.cpp
M tools/bugpoint/BugDriver.cpp
M tools/llvm-link/llvm-link.cpp
M lib/Linker/LinkModules.cpp
llvm-svn: 141606
2011-10-11 00:24:54 +00:00
fdbb7c51e9
Add support for reading many-section ELF files.
...
If you want to tackle adding the testcase, let me know. It's a 4.2MB ELF file
and I'll be happy to mail it to you.
llvm-svn: 141605
2011-10-11 00:15:42 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
98703350d0
Simplify check that optional def is there and is CPSR.
...
llvm-svn: 141602
2011-10-11 00:10:41 +00:00
de7ab801cc
Add a natural stack alignment field to TargetData, and prevent InstCombine from
...
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
llvm-svn: 141599
2011-10-10 23:42:08 +00:00
ee3be4f2a9
Fix warning.
...
llvm-svn: 141597
2011-10-10 23:36:56 +00:00
478d5bc0d0
Revert r141569 and r141576.
...
llvm-svn: 141594
2011-10-10 23:18:02 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
...
llvm-svn: 141592
2011-10-10 23:06:42 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
2957c88c0a
Add a name to sub-operand for clarity.
...
llvm-svn: 141590
2011-10-10 22:55:05 +00:00
0a10cdc704
If the CPSR is defined by a copy, then we don't want to merge it into an IT
...
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
llvm-svn: 141589
2011-10-10 22:52:53 +00:00
8ec0897db6
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
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llvm-svn: 141585
2011-10-10 22:28:47 +00:00
7989460a1f
Object: add getSectionAlignment.
...
llvm-svn: 141581
2011-10-10 21:55:43 +00:00
add0c43ebb
Give targets a chance to expand even standard pseudos.
...
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().
This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy. See the ARM -widen-vmovs option.
llvm-svn: 141578
2011-10-10 20:34:28 +00:00
2689f95875
If loop header is also loop exiting block then it may not be safe to hoist instructions.
...
llvm-svn: 141576
2011-10-10 20:32:03 +00:00
874c519337
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
...
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
814598563f
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
...
instruction set has no 64-bit SRA support.
llvm-svn: 141570
2011-10-10 19:31:45 +00:00
e554d5995b
Add dominance check for the instruction being hoisted.
...
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.
llvm-svn: 141569
2011-10-10 19:09:20 +00:00
cc6659b2ae
The Mips specific function for instruction cache invalidation cannot be
...
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic
llvm-svn: 141564
2011-10-10 18:41:02 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
bed5504f5f
MCAtom extending methods need to extend the range of the atom as well.
...
llvm-svn: 141557
2011-10-10 18:09:38 +00:00
ea662bb32f
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
a14c5723eb
Put a bunch of calls to ToggleFeature behind proper if statements.
...
llvm-svn: 141527
2011-10-10 05:34:02 +00:00
b60187ae74
Fix a regression from r138445. If we're loading from the frame/base pointer
...
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
llvm-svn: 141523
2011-10-10 01:03:35 +00:00
dd40b0d792
PTX: Print .ptr kernel attributes if PTX version >= 2.2
...
llvm-svn: 141508
2011-10-09 15:42:02 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
513d1213cc
Prevent potential NOREX bug.
...
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:
%vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2
If such a live range is ever split, its register class must not be
inflated to GR8. The sub-register copy can only target GR8_NOREX.
I dont have a test case for this theoretical bug.
llvm-svn: 141500
2011-10-08 20:20:03 +00:00
729abd360e
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
...
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
llvm-svn: 141499
2011-10-08 18:28:28 +00:00
8a984e9418
Revert r141079: tblgen: add preprocessor as a separate mode
...
llvm-svn: 141492
2011-10-08 12:39:26 +00:00
a0263e7aca
Always check if a method or a type exist before trying to create it.
...
llvm-svn: 141490
2011-10-08 11:56:36 +00:00
648b2fafd8
lib/Object: Suppress warnings on gcc-4.3.4 cygwin
...
llvm-svn: 141485
2011-10-08 11:22:53 +00:00
f995985eba
lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify.
...
llvm-svn: 141484
2011-10-08 11:22:47 +00:00
ade616cb57
Whitespace
...
llvm-svn: 141483
2011-10-08 11:22:41 +00:00
e45373520d
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
...
llvm-svn: 141481
2011-10-08 08:38:45 +00:00
6be7d6c976
Simplify definition of FP move instructions.
...
llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
...
llvm-svn: 141474
2011-10-08 03:29:22 +00:00
13ae13bdc2
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
...
conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
eef7308df6
Add an extra safety check in front of the optimization in r141442.
...
llvm-svn: 141470
2011-10-08 02:16:39 +00:00
e9574be6a3
Use the code that lowers the arguments and spills any values which are alive
...
across unwind edges. This is for the back-end which expects such things.
The code is from the original SjLj EH pass.
llvm-svn: 141463
2011-10-08 00:56:47 +00:00
159970f733
Object: Add support for opening stdin.
...
llvm-svn: 141449
2011-10-08 00:17:58 +00:00
7eb8159927
Object: constize Archive.
...
llvm-svn: 141448
2011-10-08 00:17:45 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
7fb669ab48
LSR should only reuse phis that match its formula.
...
Fixes rdar://problem/5064068
llvm-svn: 141442
2011-10-07 23:46:21 +00:00
195464184e
Fix APInt::operator*= so that it computes the correct result for large integers where there is unsigned overflow. Fix APFloat::toString so that it doesn't depend on the incorrect behavior in common cases (and computes the correct result in some rare cases). Fixes PR11086.
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llvm-svn: 141441
2011-10-07 23:40:49 +00:00
133a16871f
Don't emit the symbol table entry for the .symtab_shndx section either.
...
llvm-svn: 141440
2011-10-07 23:29:53 +00:00
c6ac5f7388
Remove extraneous curlies. No functionality change.
...
llvm-svn: 141439
2011-10-07 23:28:32 +00:00
6e5778f7b1
ARM prefix asmparser operand kind enums for readability.
...
llvm-svn: 141438
2011-10-07 23:24:09 +00:00
883ec97115
Take all of the invoke basic blocks and make the dispatch basic block their new
...
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
llvm-svn: 141436
2011-10-07 23:18:02 +00:00
f9f5e455d4
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
...
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
llvm-svn: 141419
2011-10-07 22:08:37 +00:00
7ecfbd90ef
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
...
do. This will be useful later on with the new SJLJ stuff.
llvm-svn: 141416
2011-10-07 21:25:38 +00:00
8b02d36a23
Don't emit a shstrtabindex in the reserved range. Spotted by inspection and
...
patch by Cary Coutant!
llvm-svn: 141413
2011-10-07 20:58:24 +00:00
4eb1143038
Clarify/fix typo. No functionality change.
...
llvm-svn: 141412
2011-10-07 20:56:23 +00:00
464fcc0035
Constrain both operands on MOVZX32_NOREXrr8.
...
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.
Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.
This fixes a miscompilation in 20040709-2 in the gcc test suite.
llvm-svn: 141410
2011-10-07 20:15:54 +00:00
cfb6cc7b14
Fix GCC again.
...
llvm-svn: 141389
2011-10-07 19:46:12 +00:00
e5fd004719
Change relocation API to be per section. This time without breaking GCC.
...
llvm-svn: 141385
2011-10-07 19:25:32 +00:00
Bob Wilson