Commit Graph

50770 Commits

Author SHA1 Message Date
Eli Friedman b72d55353a Add support to the old JIT for acquire/release loads and stores on x86. PR11207.
llvm-svn: 142841
2011-10-24 20:24:21 +00:00
Owen Anderson 953af053eb Stub out some of the MachO relocation decoding hooks.
llvm-svn: 142840
2011-10-24 20:19:18 +00:00
Douglas Gregor 0cc574eee7 Really unbreak CMake build
llvm-svn: 142822
2011-10-24 18:10:52 +00:00
Douglas Gregor d0800fda95 Unbreak CMake build
llvm-svn: 142821
2011-10-24 18:09:23 +00:00
Owen Anderson 295b1e84ce Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
llvm-svn: 142817
2011-10-24 18:04:29 +00:00
Dan Gohman e2ff95e327 Delete the top-down "Latency" scheduler. Top-down scheduling doesn't handle
physreg dependencies, and upcoming codegen changes will require proper
physreg dependence handling.

llvm-svn: 142816
2011-10-24 18:01:06 +00:00
Dan Gohman d78fc160cc Delete the Latency scheduling preference.
llvm-svn: 142815
2011-10-24 17:56:48 +00:00
Dan Gohman 4ed1afa51d Change this overloaded use of Sched::Latency to be an overloaded
use of Sched::ILP instead, as Sched::Latency is going away.

llvm-svn: 142813
2011-10-24 17:55:11 +00:00
Dan Gohman 2c9bda1512 Remove the explicit request for "Latency" scheduling from MSP430,
as the Latency scheduler is going away.

llvm-svn: 142811
2011-10-24 17:53:16 +00:00
Dan Gohman c32af340fc Change the default scheduler from Latency to ILP, since Latency
is going away.

llvm-svn: 142810
2011-10-24 17:45:02 +00:00
Jim Grosbach 1b5e49a35a Thumb2 LDM instructions can target PC. Make sure to encode it.
PR11220

llvm-svn: 142801
2011-10-24 17:16:24 +00:00
Bill Wendling 38f86c505c Cleanup. Get rid of the old SjLj EH lowering code. No functionality change.
llvm-svn: 142800
2011-10-24 17:12:36 +00:00
Chandler Carruth 30b63c6430 Sink an otherwise unused variable's initializer into the asserts that
used it. Fixes an unused variable warning from GCC on release builds.

llvm-svn: 142799
2011-10-24 16:51:55 +00:00
Chandler Carruth 7111f4564c Remove return heuristics from the static branch probabilities, and
introduce no-return or unreachable heuristics.

The return heuristics from the Ball and Larus paper don't work well in
practice as they pessimize early return paths. The only good hitrate
return heuristics are those for:
 - NULL return
 - Constant return
 - negative integer return

Only the last of these three can possibly require significant code for
the returning block, and even the last is fairly rare and usually also
a constant. As a consequence, even for the cold return paths, there is
little code on that return path, and so little code density to be gained
by sinking it. The places where sinking these blocks is valuable (inner
loops) will already be weighted appropriately as the edge is a loop-exit
branch.

All of this aside, early returns are nearly as common as all three of
these return categories, and should actually be predicted as taken!
Rather than muddy the waters of the static predictions, just remain
silent on returns and let the CFG itself dictate any layout or other
issues.

However, the return heuristic was flagging one very important case:
unreachable. Unfortunately it still gave a 1/4 chance of the
branch-to-unreachable occuring. It also didn't do a rigorous job of
finding those blocks which post-dominate an unreachable block.

This patch builds a more powerful analysis that should flag all branches
to blocks known to then reach unreachable. It also has better worst-case
runtime complexity by not looping through successors for each block. The
previous code would perform an N^2 walk in the event of a single entry
block branching to N successors with a switch where each successor falls
through to the next and they finally fall through to a return.

Test case added for noreturn heuristics. Also doxygen comments improved
along the way.

llvm-svn: 142793
2011-10-24 12:01:08 +00:00
Nick Lewycky 9be7f277e4 Reapply r142781 with fix. Original message:
Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
  loop header when computing the trip count.

  With this, we now constant evaluate:
    struct ListNode { const struct ListNode *next; int i; };
    static const struct ListNode node1 = {0, 1};
    static const struct ListNode node2 = {&node1, 2};
    static const struct ListNode node3 = {&node2, 3};
    int test() {
      int sum = 0;
      for (const struct ListNode *n = &node3; n != 0; n = n->next)
        sum += n->i;
      return sum;
    }

llvm-svn: 142790
2011-10-24 06:57:05 +00:00
Nick Lewycky 8e904dee82 PHI nodes not in the loop header aren't part of the loop iteration initial
state. Furthermore, they might not have two operands. This fixes the underlying
issue behind the crashes introduced in r142781.

llvm-svn: 142788
2011-10-24 05:51:01 +00:00
Nick Lewycky dd1d3df524 A dead malloc, a free(NULL) and a free(undef) are all trivially dead
instructions.

This doesn't introduce any optimizations we weren't doing before (except
potentially due to pass ordering issues), now passes will eliminate them sooner
as part of their own cleanups.

llvm-svn: 142787
2011-10-24 04:35:36 +00:00
Nick Lewycky 9d28c26d77 Speculatively revert r142781. Bots are showing
Assertion `i_nocapture < OperandTraits<PHINode>::operands(this) && "getOperand() out of range!"' failed.
coming out of indvars.

llvm-svn: 142786
2011-10-24 04:00:25 +00:00
NAKAMURA Takumi 66c9e4ffd5 Windows/Path.inc: [PR8460] Get rid of ScopedNullTerminator. Thanks to Zvi Rackover!
llvm-svn: 142785
2011-10-24 03:27:19 +00:00
Chandler Carruth 7a0094a673 Simplify the design of BranchProbabilityInfo by collapsing it into
a single class. Previously it was split between two classes, one
internal and one external. The concern seemed to center around exposing
the weights used, but those can remain confined to the implementation
file.

Having a single class to maintain the state and analyses in use will
also simplify several of the enhancements I want to make to our static
heuristics.

llvm-svn: 142783
2011-10-24 01:40:45 +00:00
Nick Lewycky 1700007ecc Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the
loop header when computing the trip count.

With this, we now constant evaluate:
  struct ListNode { const struct ListNode *next; int i; };
  static const struct ListNode node1 = {0, 1};
  static const struct ListNode node2 = {&node1, 2};
  static const struct ListNode node3 = {&node2, 3};
  int test() {
    int sum = 0;
    for (const struct ListNode *n = &node3; n != 0; n = n->next)
      sum += n->i;
    return sum;
  }

llvm-svn: 142781
2011-10-23 23:43:14 +00:00
Chandler Carruth 24cee10fb1 Tidy up a loop to be more idiomatic for LLVM's codebase, and remove some
extraneous whitespace. Trying to clean-up this pass as much as I can
before I start making functional changes.

llvm-svn: 142780
2011-10-23 22:40:13 +00:00
Craig Topper b05d9e9bea Add X86 SARX, SHRX, and SHLX instructions.
llvm-svn: 142779
2011-10-23 22:18:24 +00:00
Chandler Carruth 1c8ace0e89 Teach the BranchProbabilityInfo pass to print its results, and use that
to bring it under direct test instead of merely indirectly testing it in
the BlockFrequencyInfo pass.

The next step is to start adding tests for the various heuristics
employed, and to start fixing those heuristics once they're under test.

llvm-svn: 142778
2011-10-23 21:21:50 +00:00
Chandler Carruth fd7475e906 Now that we have comparison on probabilities, add some static functions
to get important constant branch probabilities and use them for finding
the best branch out of a set of possibilities.

llvm-svn: 142762
2011-10-23 20:10:34 +00:00
Chandler Carruth 446210b616 Remove a commented out line of code that snuck by my auditing.
llvm-svn: 142761
2011-10-23 20:10:30 +00:00
Benjamin Kramer cc0ed6ba04 Print branch probabilities as percentages.
50% is much more readable than 5.000000e-01.

llvm-svn: 142752
2011-10-23 11:32:54 +00:00
Benjamin Kramer 929f53f65c Add compare operators to BranchProbability and use it to determine if an edge is hot.
llvm-svn: 142751
2011-10-23 11:19:14 +00:00
Chandler Carruth bd1be4d01c Completely re-write the algorithm behind MachineBlockPlacement based on
discussions with Andy. Fundamentally, the previous algorithm is both
counter productive on several fronts and prioritizing things which
aren't necessarily the most important: static branch prediction.

The new algorithm uses the existing loop CFG structure information to
walk through the CFG itself to layout blocks. It coalesces adjacent
blocks within the loop where the CFG allows based on the most likely
path taken. Finally, it topologically orders the block chains that have
been formed. This allows it to choose a (mostly) topologically valid
ordering which still priorizes fallthrough within the structural
constraints.

As a final twist in the algorithm, it does violate the CFG when it
discovers a "hot" edge, that is an edge that is more than 4x hotter than
the competing edges in the CFG. These are forcibly merged into
a fallthrough chain.

Future transformations that need te be added are rotation of loop exit
conditions to be fallthrough, and better isolation of cold block chains.
I'm also planning on adding statistics to model how well the algorithm
does at laying out blocks based on the probabilities it receives.

The old tests mostly still pass, and I have some new tests to add, but
the nested loops are still behaving very strangely. This almost seems
like working-as-intended as it rotated the exit branch to be
fallthrough, but I'm not convinced this is actually the best layout. It
is well supported by the probabilities for loops we currently get, but
those are pretty broken for nested loops, so this may change later.

llvm-svn: 142743
2011-10-23 09:18:45 +00:00
Craig Topper 980d59832a Add X86 RORX instruction
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Cameron Zwarich 057fbb1a10 The element insertion code in scalar replacement doesn't handle incorrect
element types, even though the element extraction code does. It is surprising
that this bug has been here for so long. Fixes <rdar://problem/10318778>.

llvm-svn: 142740
2011-10-23 07:02:10 +00:00
Craig Topper e94d277db8 Add X86 MULX instruction for disassembler.
llvm-svn: 142738
2011-10-23 00:33:32 +00:00
Craig Topper 7412aa9886 Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
llvm-svn: 142737
2011-10-22 23:13:53 +00:00
Nick Lewycky 32f8051d66 A non-escaping malloc in the entry block is not unlike an alloca. Do dead-store
elimination on them too.

llvm-svn: 142735
2011-10-22 21:59:35 +00:00
Nick Lewycky a6674c7fc9 Make SCEV's brute force analysis stronger in two ways. Firstly, we should be
able to constant fold load instructions where the argument is a constant.
Second, we should be able to watch multiple PHI nodes through the loop; this
patch only supports PHIs in loop headers, more can be done here.

With this patch, we now constant evaluate:
  static const int arr[] = {1, 2, 3, 4, 5};
  int test() {
    int sum = 0;
    for (int i = 0; i < 5; ++i) sum += arr[i];
    return sum;
  }

llvm-svn: 142731
2011-10-22 19:58:20 +00:00
Benjamin Kramer 0d6d098841 Move various generated tables into read-only memory, fixing up const correctness along the way.
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Nadav Rotem e649d66552 Fix pr11193.
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.

llvm-svn: 142724
2011-10-22 12:39:25 +00:00
Bill Wendling 94e6643fce The different flavors of ARM have different valid subsets of registers. Check
that the set of callee-saved registers is correct for the specific platform.
<rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2

llvm-svn: 142706
2011-10-22 00:29:28 +00:00
Jim Grosbach 11c0b347c6 Assembly parsing for 4-register sequential variant of VLD2.
llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach 118b38cbf1 Assembly parsing for 2-register sequential variant of VLD2.
llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Bill Wendling b1c430886b Make sure that the landing pads themselves have no PHI instructions in them.
The assumption in the back-end is that PHIs are not allowed at the start of the
landing pad block for SjLj exceptions.
<rdar://problem/10313708>

llvm-svn: 142689
2011-10-21 22:08:56 +00:00
Benjamin Kramer 606a50a9f8 Extend the floating point heuristic to consider NaN checks unlikely.
llvm-svn: 142687
2011-10-21 21:13:47 +00:00
Eli Friedman 688db1d6d0 Remap blockaddress correctly when inlining a function. Fixes PR10162.
llvm-svn: 142684
2011-10-21 20:45:19 +00:00
Owen Anderson 500ebeb87f Use LLVMBool for a function that logically returns a boolean value.
llvm-svn: 142683
2011-10-21 20:35:58 +00:00
Jim Grosbach 846bcff7c7 Assembly parsing for 4-register variant of VLD1.
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Benjamin Kramer 1e731a10d0 BranchProbabilityInfo: floating point equality is unlikely.
This is from the same paper from Ball and Larus as the rest of the currently implemented heuristics.

llvm-svn: 142677
2011-10-21 20:12:47 +00:00
Jim Grosbach c4360fe575 Assembly parsing for 3-register variant of VLD1.
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Owen Anderson cef5641982 STABS symbols are debug symbols.
llvm-svn: 142673
2011-10-21 19:26:54 +00:00
Eli Friedman 303c81c773 Minor simplification: use ShuffleVectorInst::getMaskValue instead of a more expensive helper.
llvm-svn: 142672
2011-10-21 19:11:34 +00:00
Eli Friedman ce818277fc Extend instcombine's shufflevector simplification to handle more cases where the input and output vectors have different sizes. Patch by Xiaoyi Guo.
llvm-svn: 142671
2011-10-21 19:06:29 +00:00
Jim Grosbach 2f2e3c4737 ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Owen Anderson 03a173eb71 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing.
llvm-svn: 142669
2011-10-21 18:43:28 +00:00
Owen Anderson 07bfdbb233 Bind libObject API for obtaining the section containing a Symbol.
llvm-svn: 142667
2011-10-21 18:21:22 +00:00
Owen Anderson f239db40d5 Expand the coverage of the libObject C bindings to include more SectionRef accessors as well as Symbol iterators.
llvm-svn: 142661
2011-10-21 17:50:59 +00:00
Nadav Rotem 5e00bb5feb Fix pr11194. When promoting and splitting integers we need to use
ZExtPromotedInteger and SExtPromotedInteger based on the operation we legalize.

SetCC return type needs to be legalized via PromoteTargetBoolean.

llvm-svn: 142660
2011-10-21 17:35:19 +00:00
Jim Grosbach e6d88c9a51 Nuke an #if0 that got accidentally left in.
llvm-svn: 142658
2011-10-21 16:59:08 +00:00
Jim Grosbach 20cb505e2f whitespace.
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
Jim Grosbach e3013dd62d Remove some outdated comments.
llvm-svn: 142653
2011-10-21 16:14:12 +00:00
Nadav Rotem d315157f12 1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type.
2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1.

llvm-svn: 142648
2011-10-21 11:42:07 +00:00
Anton Korobeynikov b27f11e01d Fix build on mingw-w64.
Patch by Ruben Van Boxem!

llvm-svn: 142646
2011-10-21 09:38:50 +00:00
Chandler Carruth 8b9737cb54 Add loop aligning to MachineBlockPlacement based on review discussion so
it's a bit more plausible to use this instead of CodePlacementOpt. The
code for this was shamelessly stolen from CodePlacementOpt, and then
trimmed down a bit. There doesn't seem to be much utility in returning
true/false from this pass as we may or may not have rewritten all of the
blocks. Also, the statistic of counting how many loops were aligned
doesn't seem terribly important so I removed it. If folks would like it
to be included, I'm happy to add it back.

This was probably the most egregious of the missing features, and now
I'm going to start gathering some performance numbers and looking at
specific loop structures that have different layout between the two.

Test is updated to include both basic loop alignment and nested loop
alignment.

llvm-svn: 142645
2011-10-21 08:57:37 +00:00
Craig Topper 039a79067a Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.
llvm-svn: 142642
2011-10-21 06:55:01 +00:00
Chandler Carruth 1028142564 Implement a block placement pass based on the branch probability and
block frequency analyses. This differs substantially from the existing
block-placement pass in LLVM:

1) It operates on the Machine-IR in the CodeGen layer. This exposes much
   more (and more precise) information and opportunities. Also, the
   results are more stable due to fewer transforms ocurring after the
   pass runs.
2) It uses the generalized probability and frequency analyses. These can
   model static heuristics, code annotation derived heuristics as well
   as eventual profile loading. By basing the optimization on the
   analysis interface it can work from any (or a combination) of these
   inputs.
3) It uses a more aggressive algorithm, both building chains from tho
   bottom up to maximize benefit, and using an SCC-based walk to layout
   chains of blocks in a profitable ordering without O(N^2) iterations
   which the old pass involves.

The pass is currently gated behind a flag, and not enabled by default
because it still needs to grow some important features. Most notably, it
needs to support loop aligning and careful layout of loop structures
much as done by hand currently in CodePlacementOpt. Once it supports
these, and has sufficient testing and quality tuning, it should replace
both of these passes.

Thanks to Nick Lewycky and Richard Smith for help authoring & debugging
this, and to Jakob, Andy, Eric, Jim, and probably a few others I'm
forgetting for reviewing and answering all my questions. Writing
a backend pass is *sooo* much better now than it used to be. =D

llvm-svn: 142641
2011-10-21 06:46:38 +00:00
Chandler Carruth 001153784a Remove a now dead function, fixing -Wunused-function warnings from
Clang.

llvm-svn: 142631
2011-10-21 01:23:41 +00:00
Richard Smith c842c2ffe2 Fix unused variable warning.
llvm-svn: 142630
2011-10-21 01:22:04 +00:00
Owen Anderson 16c8fc5191 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
llvm-svn: 142626
2011-10-20 22:23:58 +00:00
David Meyer a93b4bc98c Remove unused include of sys/uio.h in MemoryBuffer.cpp. It was not correctly protected by ifdef either.
llvm-svn: 142623
2011-10-20 21:57:46 +00:00
Dan Gohman 000e2add18 Disable the PPC hazard recognizer. It currently only supports
top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621
2011-10-20 21:45:36 +00:00
Dan Gohman 90fb55237b Delete the list-tdrr scheduler. Top-down schedulers are going away
because they don't support physical register dependencies.

llvm-svn: 142620
2011-10-20 21:44:34 +00:00
Owen Anderson 3acac94b60 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
llvm-svn: 142618
2011-10-20 21:24:38 +00:00
Bill Wendling cf7bdf4438 Add missing operand. <rdar://problem/10313323>
llvm-svn: 142615
2011-10-20 20:37:11 +00:00
Lang Hames aaf379027d Haven't yet found a nice way to handle TargetData verification in the
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605
2011-10-20 19:24:44 +00:00
Chad Rosier 4236a63c3c Revert r142579, "Fix a type in the legalization of CONCAT_VECTORS". This is
causing one of the unit tests to infinitely loop, which resulted in the 
buildbots stalling.

llvm-svn: 142604
2011-10-20 19:19:10 +00:00
Devang Patel 1d8ab465bf As Evan suggested, loads from constant pool are safe to speculate.
llvm-svn: 142593
2011-10-20 17:42:23 +00:00
Devang Patel 830c776a94 Add a comment.
llvm-svn: 142592
2011-10-20 17:31:18 +00:00
Jim Grosbach 79ebc51c45 Tidy up. Trailing whitespace.
llvm-svn: 142591
2011-10-20 17:28:20 +00:00
Jim Grosbach 9036c5cf2b ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
llvm-svn: 142583
2011-10-20 15:04:25 +00:00
Jim Grosbach 8db25984a9 ARM VTBX (one register) assembly parsing and encoding.
llvm-svn: 142581
2011-10-20 14:48:50 +00:00
Nadav Rotem fe3969293d Fix a type in the legalization of CONCAT_VECTORS.
llvm-svn: 142579
2011-10-20 13:38:16 +00:00
Eli Friedman 1923a330e6 Refactor code from inlining and globalopt that checks whether a function definition is unused, and enhance it so it can tell that functions which are only used by a blockaddress are in fact dead. This probably doesn't happen much on most code, but the Linux kernel's _THIS_IP_ can trigger this issue with blockaddress. (GlobalDCE can also handle the given tescase, but we only run that at -O3.) Found while looking at PR11180.
llvm-svn: 142572
2011-10-20 05:23:42 +00:00
Eli Friedman 68db4c2699 A FIXME about block addresses and indirectbr.
llvm-svn: 142569
2011-10-20 04:05:33 +00:00
Eli Friedman f0bb0c2934 Simplify; no intended functional change.
llvm-svn: 142567
2011-10-20 03:23:14 +00:00
Nick Lewycky 462098824f "@string = constant i8 0" is a value i8* string of length zero. Analyze that
correctly in GetStringLength, fixing PR11181!

llvm-svn: 142558
2011-10-20 00:34:35 +00:00
Chad Rosier add38c12b8 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(
llvm-svn: 142557
2011-10-20 00:07:12 +00:00
Devang Patel 88b4fa21c8 Initialze ScalarEvalution dependency.
Patch by Pranav Bhandarkar!

llvm-svn: 142556
2011-10-19 23:56:07 +00:00
Evan Cheng 54d678fff4 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355
llvm-svn: 142550
2011-10-19 22:22:54 +00:00
Nadav Rotem 8824472a25 Improve code generation for vselect on SSE2:
When checking the availability of instructions using the TLI, a 'promoted'
instruction IS available. It means that the value is bitcasted to another type
for which there is an operation. The correct check for the availablity of an
instruction is to check if it should be expanded.

llvm-svn: 142542
2011-10-19 20:43:16 +00:00
Rafael Espindola e0d0908356 Fix parsing of a line with only a # in it.
llvm-svn: 142537
2011-10-19 18:48:52 +00:00
James Molloy 2d768fd379 Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
2011-10-19 14:11:07 +00:00
David Greene 8e85b480d5 Implement Paste
Add a paste operator '#' to take two identifier-like strings and joint
them.  Internally paste gets represented as a !strconcat() with any
necessary casts to string added.

This will be used to implement basic for loop functionality as in:

for i = [0, 1, 2, 3, 4, 5, 6, 7] {
  def R#i : Register<...>
}

llvm-svn: 142525
2011-10-19 13:04:43 +00:00
David Greene 8bf0d72f0e Process NAME
During multiclass def instantiation, replace NAME in any expressions
with the value of the def or defm ID.

llvm-svn: 142524
2011-10-19 13:04:35 +00:00
David Greene 5d5d88cc1a Process Defm Prefix as Init
Parse and process a defm prefix as an Init expression.  This allows
paste operations to create defm prefixes.

llvm-svn: 142523
2011-10-19 13:04:31 +00:00
David Greene 2affd67b51 Parse Def ID as Value
Allow def and defm IDs to be general values.  We need this for paste
functionality.

llvm-svn: 142522
2011-10-19 13:04:29 +00:00
David Greene b8a7c9d0bf Don't Parse Object Body as a Name
Stop parsing a value if we are in name parsing mode and we see a left
brace.  A left brace indicates the start of an object body when we are
parsing a name.

llvm-svn: 142521
2011-10-19 13:04:26 +00:00
David Greene 232bd6017c Use Parse Mode
Augment the value parser to respect the parse mode and not error if an
ID doesn't map to an object and we are in name parsing mode.

llvm-svn: 142520
2011-10-19 13:04:21 +00:00
David Greene d4263a6ad0 Make ID Parsing More Flexible
Add a mode control to value and ID parsers.  The two modes are:

- Parse a value.  Expect the parsed ID to map to an existing object.

- Parse a name.  Expect the parsed ID to not map to any existing object.

The first is used when parsing an identifier to be looked up, for
example a record field or template argument.  The second is used for
parsing declarations.  Paste functionality implies that declarations
can contain arbitrary expressions so we need to be able to call into
the general value parser to parse declarations with paste operators.
So we need a way to parse a value-like thing without expecting that
the result will map to some existing object.  This parse mode provides
that.

llvm-svn: 142519
2011-10-19 13:04:20 +00:00
David Greene d699161a99 Add NAME Member
Add a Value named "NAME" to each Record.  This will be set to the def or defm
name when instantiating multiclasses.  This will replace the #NAME# processing
hack once paste functionality is in place.

llvm-svn: 142518
2011-10-19 13:04:13 +00:00
David Greene 7b6e641144 Fix Name Access
Get the Record name as a string explicitly to avoid asserts.

llvm-svn: 142517
2011-10-19 13:04:02 +00:00
David Greene 8eed9988b1 Fix Name Access
Get the Record name as a string explicitly to avoid asserts.

llvm-svn: 142516
2011-10-19 13:03:58 +00:00
David Greene 07e055f919 Fix Name Access
Get the Record name as a string explicitly to avoid asserts.

llvm-svn: 142515
2011-10-19 13:03:51 +00:00
David Greene 3a20f5a687 Fix Name Access
Get the Record name by string explicitly to avoid potential asserts.

llvm-svn: 142514
2011-10-19 13:03:45 +00:00
David Greene 5c9fa026dc Disambiguate Numbers and Identifiers
Use lookahead to determine whether a number is really a number or is
part of something forming an identifier.  This won't come into play
until the paste operator is recognized as a unique token.

llvm-svn: 142513
2011-10-19 13:03:39 +00:00
David Greene 9ba42085da Add Peek
Add a peek function to let the Lexer look at a character arbitrarily
far ahead in the stream without consuming anything.  We need this to
disambiguate numbers and operands of a paste operation.  For example:

def foo#8i

Without lookahead the lexer will treat '8' as a number rather than as
part of a string to be pasted to form an identifier.

llvm-svn: 142512
2011-10-19 13:03:35 +00:00
David Greene 9effff28c8 Resolve Record Names
When resolving Record values, be sure to update the Record name as it
may contain references to the value.

llvm-svn: 142511
2011-10-19 13:03:30 +00:00
David Greene f651a2a5c0 Allow Names Changes on Unregistered Records
Add Record names to be changed even on Records that aren't yet
registered.  We need to be able to do this for paste functionality
because we do not want to register def names before they are unique
and that can only happen once all paste operations are done.  This
change lets us update Record names formed by paste operations and
register the result later.

llvm-svn: 142510
2011-10-19 13:03:25 +00:00
David Greene 077d84e6f3 Fix Name Access
Ask for the Record name as a string explicitly to avoid a possible assert.

llvm-svn: 142506
2011-10-19 13:03:02 +00:00
David Greene 98be78aeea Fix Name Access
Ask for the Record name as a string explicitly to avoid a possible
assert.

llvm-svn: 142505
2011-10-19 13:02:57 +00:00
David Greene 658a4b71b6 Fix Name Access
Ask for the record name as a string explicitly to avoid a potential
assert.

llvm-svn: 142504
2011-10-19 13:02:52 +00:00
David Greene b77fc0d906 Add Record Init
Add an init function to be shared among Record constructors.

llvm-svn: 142501
2011-10-19 13:02:45 +00:00
David Greene db10e69138 Make Template Arg Names Inits
Allow template arg names to be Inits.  This is further work to
implement paste as it allows template names to participate in paste
operations.

llvm-svn: 142500
2011-10-19 13:02:42 +00:00
David Greene 3ca42126f5 Let SetValue Take and Init Name
Convert SetValue to take the value name as an Init.  This allows us to
set values for variables whose names are not yet fully resolved.

llvm-svn: 142499
2011-10-19 13:02:39 +00:00
David Greene e714512cb6 Add Utility to Scope Names
Add a couple of utility functions to take a variable name and qualify
it with the namespace of the enclosing class and/or multiclass.  This
is inpreparation for making template arg names first-class Inits.

llvm-svn: 142498
2011-10-19 13:02:36 +00:00
David Greene 914adf0ecb Make VarInit Name an Init
Make the VarInit name an Init itself.  We need this to implement paste
functionality so we can reference variables whose names are not yet
completely resolved.

llvm-svn: 142497
2011-10-19 13:02:33 +00:00
David Greene 28438acd46 Add Value Accessors
Add accessors to get Record values by Init name.  This lets us look up
Record values whose names are not yet fully resolved.  More work
toward paste.

llvm-svn: 142496
2011-10-19 13:02:29 +00:00
Chandler Carruth deac50cba9 Generalize the reading of probability metadata to work for both branches
and switches, with arbitrary numbers of successors. Still optimized for
the common case of 2 successors for a conditional branch.

Add a test case for switch metadata showing up in the BlockFrequencyInfo pass.

llvm-svn: 142493
2011-10-19 10:32:19 +00:00
Chandler Carruth d27a7a947b Teach the BranchProbabilityInfo analysis pass to read any metadata
encoding of probabilities. In the absense of metadata, it continues to
fall back on static heuristics.

This allows __builtin_expect, after lowering through llvm.expect
a branch instruction's metadata, to actually enter the branch
probability model. This is one component of resolving PR2577.

llvm-svn: 142492
2011-10-19 10:30:30 +00:00
Chandler Carruth 343fad44ea Add pass printing support to BlockFrequencyInfo pass. The implementation
layer already had support for printing the results of this analysis, but
the wiring was missing.

Now that printing the analysis works, actually bring some of this
analysis, and the BranchProbabilityInfo analysis that it wraps, under
test! I'm planning on fixing some bugs and doing other work here, so
having a nice place to add regression tests and a way to observe the
results is really useful.

llvm-svn: 142491
2011-10-19 10:12:41 +00:00
Nadav Rotem 6652e22bad Add support for the vector-widening of vselect and vector-setcc
llvm-svn: 142488
2011-10-19 09:45:11 +00:00
Bill Wendling 2977a15ab1 Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool.
llvm-svn: 142485
2011-10-19 09:24:02 +00:00
Bill Wendling 7c1634556d Remove some dead code.
llvm-svn: 142484
2011-10-19 09:04:11 +00:00
Craig Topper ef309c3384 Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
llvm-svn: 142480
2011-10-19 07:48:35 +00:00
Joe Abbey c39977d01b Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete.
llvm-svn: 142464
2011-10-19 00:13:13 +00:00
Bill Wendling 94f60018e0 Emit the MOVT instruction only if the # LPads is > 64K.
llvm-svn: 142460
2011-10-18 23:19:55 +00:00
Bill Wendling 64e6bfc16c For Thumb mode, we need to use a constant pool if the value is too large to be
used with the CMP instruction.

llvm-svn: 142458
2011-10-18 23:11:05 +00:00
Eric Christopher 16ec8c103a Revert "Turn on the vzeroupper pass by default."
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455
2011-10-18 23:10:11 +00:00
Jim Grosbach ad47cfcef9 ARM VTBL (one register) assembly parsing and encoding.
llvm-svn: 142441
2011-10-18 23:02:30 +00:00
Bill Wendling 4969dcdef9 Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
2011-10-18 22:52:20 +00:00
Eric Christopher 9bede2dd92 Turn on the vzeroupper pass by default.
I'll remove/rename the option in a few days.

llvm-svn: 142439
2011-10-18 22:50:17 +00:00
Bill Wendling 85833f71c6 Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
2011-10-18 22:49:07 +00:00
Nick Lewycky ac4c1860a3 Missed a spot!
llvm-svn: 142436
2011-10-18 22:40:18 +00:00
Nick Lewycky 5ca33ac926 Fix some typo/formatting issues. No functionality change.
llvm-svn: 142435
2011-10-18 22:39:43 +00:00
Nadav Rotem 75c2229f41 Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero.
llvm-svn: 142434
2011-10-18 22:32:43 +00:00
Lang Hames 7d2f7b5a33 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>.
llvm-svn: 142432
2011-10-18 22:11:33 +00:00
Bill Wendling 973c817cde The value we're comparing against may be too large for the ARM CMP
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
2011-10-18 22:11:18 +00:00
Bill Wendling b2a703d352 The immediate may be too large for the CMP instruction. Move it into a register
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
2011-10-18 21:55:58 +00:00
Jim Grosbach 6918617e32 Yet more ARM NEON assembly parsing for the lane index operand.
llvm-svn: 142416
2011-10-18 20:21:17 +00:00
Jim Grosbach e9f204c197 ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
Jim Grosbach 712f3670fd ARM vmov assembly parsing for the lane index operand.
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
Jim Grosbach 05c562f094 The MCJITMemoryManager takes ownership of the JMM, so don't leak it.
llvm-svn: 142410
2011-10-18 19:57:38 +00:00
Michael J. Spencer 443410d722 Object/COFF: Remove useless test.
llvm-svn: 142408
2011-10-18 19:51:36 +00:00
Michael J. Spencer 097be9f63c Object/COFF: Change type from a struct to a uint16_t. The struct would be
incorrect for bigendian systems.

llvm-svn: 142403
2011-10-18 19:31:59 +00:00
Andrew Trick 88b2450adc Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397
2011-10-18 19:18:52 +00:00
Bob Wilson 93b0f7b319 Use isIntN and isUIntN to check for valid signed/unsigned numbers.
llvm-svn: 142395
2011-10-18 18:46:49 +00:00
Andrew Trick 3f07c429b5 whitespace
llvm-svn: 142394
2011-10-18 18:40:53 +00:00
Bill Wendling 617075fcf6 A landing pad could have more than one predecessor. In that case, we want that
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390
2011-10-18 18:30:49 +00:00
Jim Grosbach 611450071c ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
Jim Grosbach c8eff0327a ARM vqdmulh assembly parsing for the lane index operand.
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
Jim Grosbach e6fbca3a61 ARM vmul assembly parsing for the lane index operand.
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes 2312a3aaa0 Final patch that completes old JIT support for Mips:
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
2011-10-18 17:50:36 +00:00
Bob Wilson 9258b76d8d Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>

llvm-svn: 142371
2011-10-18 17:34:51 +00:00