Commit Graph

48611 Commits

Author SHA1 Message Date
Argyrios Kyrtzidis 348937de07 Add an optional 'bool makeAbsolute' in llvm::sys::fs::unique_file function.
If true and 'model' parameter is not an absolute path, a temp directory will be prepended.
Make it true by default to match current behaviour.

llvm-svn: 136310
2011-07-28 00:29:20 +00:00
Owen Anderson b81af2abe0 Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
llvm-svn: 136295
2011-07-27 23:36:57 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Kevin Enderby 5ef6c453a6 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
2011-07-27 22:34:17 +00:00
Eli Friedman 26a484852e Code generation for 'fence' instruction.
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
Jakub Staszak da3df4302a Use BlockFrequency instead of uint32_t in BlockFrequencyInfo.
llvm-svn: 136278
2011-07-27 22:05:51 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
2011-07-27 22:01:42 +00:00
Devang Patel 53dc616170 Remove outdated FIXME comment.
llvm-svn: 136275
2011-07-27 22:00:01 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
2011-07-27 21:58:11 +00:00
Bill Wendling 9c5b7ff807 Refuse to inline two functions which use different personality functions.
llvm-svn: 136269
2011-07-27 21:44:28 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Owen Anderson fa9e6d43a0 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
llvm-svn: 136255
2011-07-27 20:29:48 +00:00
Bill Wendling 6c923bb8d9 Merge the contents from exception-handling-rewrite to the mainline.
This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253
2011-07-27 20:18:04 +00:00
Jim Grosbach 833b9d3353 ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Nick Lewycky 8ac9ecedfd Teach the ConstantMerge pass about alignment. Fixes PR10514!
llvm-svn: 136250
2011-07-27 19:47:34 +00:00
Eli Friedman e6d1853e74 X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.
llvm-svn: 136249
2011-07-27 19:43:50 +00:00
Jim Grosbach 66ee037863 ARM assembly parsing aliases for extend instructions w/o rotate.
llvm-svn: 136229
2011-07-27 18:19:32 +00:00
Jim Grosbach 38b5503d21 ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.

llvm-svn: 136226
2011-07-27 17:48:13 +00:00
Jim Grosbach 8b31ef50c0 ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
2011-07-27 16:47:19 +00:00
Jakub Staszak 9b8a6a3b2b Optimize 96-bit division a little bit.
llvm-svn: 136222
2011-07-27 16:00:40 +00:00
Jakub Staszak a9e8aa0482 Move static methods to the anonymous namespace.
llvm-svn: 136221
2011-07-27 15:51:51 +00:00
Frits van Bommel ec9cd83905 Trim includes.
llvm-svn: 136218
2011-07-27 15:20:06 +00:00
Jeffrey Yasskin 6381c0100b Explicitly cast narrowing conversions inside {}s that will become errors in
C++0x.

llvm-svn: 136211
2011-07-27 06:22:51 +00:00
Dan Gohman 456b1edd0d Revert r136156, which broke several buildbots.
llvm-svn: 136206
2011-07-27 01:10:27 +00:00
Eli Friedman 89b694b096 Misc mid-level changes for new 'fence' instruction.
llvm-svn: 136205
2011-07-27 01:08:30 +00:00
Eli Friedman 8b5277c6cf Minor simplification.
llvm-svn: 136202
2011-07-27 01:02:25 +00:00
Bruno Cardoso Lopes f9324f4f6b Move some code around to open opportunity for more shuffle matching
llvm-svn: 136201
2011-07-27 00:56:37 +00:00
Bruno Cardoso Lopes 27a30a7792 The vpermilps and vpermilpd have different behaviour regarding the
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

llvm-svn: 136200
2011-07-27 00:56:34 +00:00
Bruno Cardoso Lopes db5fb91491 Remove more dead code!
llvm-svn: 136199
2011-07-27 00:56:27 +00:00
Eli Friedman ae8161e774 Fix AliasSetTracker so that it doesn't make any assumptions about instructions it doesn't know about (like the atomic instructions I'm adding).
llvm-svn: 136198
2011-07-27 00:46:46 +00:00
Evan Cheng 481ebb0133 Support .code32 and .code64 in X86 assembler.
llvm-svn: 136197
2011-07-27 00:38:12 +00:00
Devang Patel f098ce2757 It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry.
llvm-svn: 136196
2011-07-27 00:34:13 +00:00
Jakob Stoklund Olesen dab4b9a4b2 Add support for multi-way live range splitting.
When splitting global live ranges, it is now possible to split for
multiple destination intervals at once. Previously, we only had the main
and stack intervals.

Each edge bundle is assigned to a split candidate, and splitAroundRegion
will insert copies between the candidate intervals and the stack
interval as needed.

The multi-way splitting is used to split around compact regions when
enabled with -compact-regions. The best candidate register still gets
all the bundles it wants, but everything outside the main interval is
first split around compact regions before we create single-block
intervals.

Compact region splitting still causes some regressions, so it is not
enabled by default.

llvm-svn: 136186
2011-07-26 23:41:46 +00:00
Jakob Stoklund Olesen b1459dbc25 Print out the MBB live-in registers.
llvm-svn: 136178
2011-07-26 23:12:08 +00:00
Jakob Stoklund Olesen c3bcb02154 Eliminate copies of undefined values during coalescing.
These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.

This fixes PR10503.

llvm-svn: 136174
2011-07-26 23:00:24 +00:00
Benjamin Kramer 124ac2b997 Add a neat little two's complement hack for x86.
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

llvm-svn: 136167
2011-07-26 22:42:13 +00:00
Bruno Cardoso Lopes f8fe47bd2b Recognize unpckh* masks and match 256-bit versions. The new versions are
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

llvm-svn: 136157
2011-07-26 22:03:40 +00:00
Dan Gohman 9eb62cd159 Delete unnecessarily cautious LastCALLSEQ code.
llvm-svn: 136156
2011-07-26 22:00:59 +00:00
Jim Grosbach a5f7a8cfde ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154
2011-07-26 21:44:37 +00:00
Jim Grosbach d2659138da ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Eli Friedman 93dc04d5ca Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130.
llvm-svn: 136148
2011-07-26 21:02:58 +00:00
Evan Cheng 2833ad13f0 Remove one last reference to Target in MC library.
llvm-svn: 136145
2011-07-26 20:57:44 +00:00
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Nicolas Geoffray 84c7b9e586 Update generated code to use new API of GetElementPtrInst::Create.
llvm-svn: 136138
2011-07-26 20:52:25 +00:00
Jim Grosbach 0d6022da6b Fix over-zealous rename from r136095.
llvm-svn: 136132
2011-07-26 20:41:24 +00:00
Eli Friedman 06b8b571b2 Add obvious missing case to switch. PR10497.
llvm-svn: 136130
2011-07-26 20:38:49 +00:00
Bill Wendling 3fe5d68563 Use the correct for for the version. It's little endian and my brain is
obviously big endian. :-)
PR10502

llvm-svn: 136111
2011-07-26 18:31:41 +00:00
Jim Grosbach edaa35ae6f ARM diagnostics for ldrexd/stredx out of order paired register operands.
llvm-svn: 136110
2011-07-26 18:25:39 +00:00
Bruno Cardoso Lopes 53bc328071 Remove now unused patterns. 0 insertions(+), 98 deletions(-)
llvm-svn: 136109
2011-07-26 18:22:39 +00:00