2712d4a3d8
AMDGPU: Select mulhi 24-bit instructions
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llvm-svn: 279902
2016-08-27 01:32:27 +00:00
0486f739a4
AMDGPU/R600: Convert buffer id to VTX_READ input
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Use patterns instead of multiple instructions
Add buffer id to asm string
https://reviews.llvm.org/D22650
llvm-svn: 278749
2016-08-15 21:38:30 +00:00
4c519d3518
AMDGPU/R600: Replace barrier intrinsics
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llvm-svn: 275870
2016-07-18 18:34:59 +00:00
2fa28c330c
AMDGPU/R600: Add implicitarg.ptr intrinsic
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Differential Revision: http://reviews.llvm.org/D21622
llvm-svn: 275024
2016-07-10 21:20:29 +00:00
4a105d73a9
AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loads
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This moves of the r600 logic out of isGlobalLoad() and into the
TableGen files.
Differential Revision: http://reviews.llvm.org/D21710
llvm-svn: 274527
2016-07-05 00:12:51 +00:00
81f1b30035
AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)
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Reviewers: tstellard
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D19785
llvm-svn: 269473
2016-05-13 20:39:16 +00:00
295875efda
AMDGPU: Remove 24-bit intrinsics
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The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.
llvm-svn: 259180
2016-01-29 10:05:16 +00:00
ee0930821a
AMDGPU: Remove random TGSI intrinsic
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I don't think this was ever used.
llvm-svn: 258514
2016-01-22 18:42:44 +00:00
de5fbe9c60
AMDGPU: Pattern match ffbh pattern to instruction.
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The hardware instruction's output on 0 is -1 rather than 32.
Eliminate a test and select to -1. This removes an extra instruction
from the compatability function with HSAIL's firstbit instruction.
llvm-svn: 257352
2016-01-11 17:02:00 +00:00
e0e582c9aa
AMDGPU: Add MEM_RAT STORE_TYPED.
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v2: Add test (Matt).
Fix capitalization of isEOP (Matt).
Move pattern to class parameter (Matt).
Make the instruction available to Cayman (Matt).
Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED.
Patch by: Zoltan Gilian
llvm-svn: 249042
2015-10-01 17:51:34 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Matt Arsenault