7d4038dd88
use ArgOperand API
...
llvm-svn: 106946
2010-06-26 12:17:21 +00:00
c2ac8c4261
use ArgOperand API
...
llvm-svn: 106945
2010-06-26 12:09:10 +00:00
83205af3fa
use ArgOperand API
...
llvm-svn: 106944
2010-06-26 11:51:52 +00:00
8cfa7713e9
Followup to r106770: actually generate SXTB and SXTH for sign-extensions.
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llvm-svn: 106940
2010-06-26 04:36:50 +00:00
0248da9db4
Add support for encoding NEON VMOV (from scalar to core register) instructions.
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llvm-svn: 106938
2010-06-26 04:07:15 +00:00
b71233f34d
It's now possible to run code placement pass for ARM.
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llvm-svn: 106935
2010-06-26 01:52:05 +00:00
d7d0d4e882
When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
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CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.
Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).
This fixes PR7312.
llvm-svn: 106934
2010-06-26 00:39:23 +00:00
b4d39841e4
Renumber NEON instruction formats to be consecutive.
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llvm-svn: 106927
2010-06-26 00:05:09 +00:00
cc386fb125
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
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"N..." instead of "NEON..." for consistency with the other NEON format names.
llvm-svn: 106921
2010-06-25 23:56:05 +00:00
74d716b9cd
Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions
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llvm-svn: 106917
2010-06-25 23:47:23 +00:00
d66f66a5cf
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
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Renumber MiscFrm to 25.
llvm-svn: 106916
2010-06-25 23:45:37 +00:00
83651094ad
Reapply r106896:
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Add several AVX MOV flavors
Support VEX encoding for MRMDestReg
llvm-svn: 106912
2010-06-25 23:33:42 +00:00
acbdf53db4
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
...
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.
llvm-svn: 106908
2010-06-25 23:14:54 +00:00
4530fed87e
revert this now, it's using avx instead of sse :)
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llvm-svn: 106906
2010-06-25 23:04:29 +00:00
02b184de5b
Change if-conversion block size limit checks to add some flexibility.
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llvm-svn: 106901
2010-06-25 22:42:03 +00:00
2530ca0647
Add support for encoding 3-register NEON instructions, and fix
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emitNEON2RegInstruction's handling of 2-address operands.
llvm-svn: 106900
2010-06-25 22:40:46 +00:00
a34d9b6d84
Add several AVX MOV flavors
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Support VEX encoding for MRMDestReg
llvm-svn: 106896
2010-06-25 22:27:51 +00:00
ce97d55ad9
The hasMemory argument is irrelevant to how the argument
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for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
llvm-svn: 106893
2010-06-25 21:55:36 +00:00
e70c8b150b
Add support for encoding 2-register NEON instructions.
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llvm-svn: 106891
2010-06-25 21:17:19 +00:00
8de1fe3ccf
pcmpeqd and friends are Commutable.
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llvm-svn: 106886
2010-06-25 21:05:35 +00:00
574f68f815
Fix indentation.
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llvm-svn: 106881
2010-06-25 20:54:44 +00:00
e41e40f689
- Reapply r106066 now that the bzip2 build regression has been fixed.
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- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
2010-06-25 20:48:10 +00:00
553fafc6ce
Move the last piece of SSE2 convert instructions to the Convert Instructions section
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llvm-svn: 106877
2010-06-25 20:29:27 +00:00
62d1403a03
More SSE refactoring, this time with different types of MOVs
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llvm-svn: 106876
2010-06-25 20:22:12 +00:00
ba3ece6f27
IT instructions are considered to be scheduling hazards, but are scheduled
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with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.
Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.
llvm-svn: 106871
2010-06-25 18:43:14 +00:00
e76c0b13b9
Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
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llvm-svn: 106867
2010-06-25 18:06:22 +00:00
07aead2f8d
Add missing ARM and Thumb data layout info for vector types.
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Radar 8128745.
llvm-svn: 106820
2010-06-25 04:41:08 +00:00
eadbf9732f
Reduce indentation.
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llvm-svn: 106819
2010-06-25 04:12:31 +00:00
cbdcce6478
Add some AVX convert instructions
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llvm-svn: 106815
2010-06-25 00:39:30 +00:00
447735aa98
Refactoring of SSE convert intrinsics
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llvm-svn: 106808
2010-06-24 23:37:07 +00:00
78827d1952
Refactoring of SSE conversion instructions
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llvm-svn: 106804
2010-06-24 22:22:21 +00:00
6b6b605917
Refactor SSE cmp intrinsics and declare the same for AVX
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llvm-svn: 106796
2010-06-24 22:04:40 +00:00
4398fd7b83
- Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}.
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- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.
llvm-svn: 106787
2010-06-24 20:48:23 +00:00
5ad5226c58
Disallow matching "i" constraint to symbol addresses when
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address requires a register or secondary load to compute
(most PIC modes). This improves "g" constraint handling. 8015842.
The test from 2007 is attempting to test the fix for PR1761,
but since -relocation-model=static doesn't work on Darwin
x86-64, it was not testing what it was supposed to be testing
and was passing erroneously. Fixed to use Linux x86-64.
llvm-svn: 106779
2010-06-24 20:14:51 +00:00
c26e2f4b70
Oops. IT block formation pass needs to be run at any optimization level.
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llvm-svn: 106775
2010-06-24 19:10:14 +00:00
246c41d93e
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
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llvm-svn: 106770
2010-06-24 18:20:04 +00:00
279e55fb2e
PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
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form so they can be narrowed to 16-bit instructions.
llvm-svn: 106762
2010-06-24 16:50:20 +00:00
600f62b3ba
Reapply r106634, now that the bug it exposed is fixed.
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llvm-svn: 106746
2010-06-24 14:30:44 +00:00
8048662539
Teach the x86 mc assembler that %dr6 = %db6, this implements
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rdar://8013734
llvm-svn: 106725
2010-06-24 07:29:18 +00:00
c4e84309c4
more cleanups
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llvm-svn: 106724
2010-06-24 07:18:14 +00:00
056fd06c5f
reduce indentation
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llvm-svn: 106723
2010-06-24 07:16:25 +00:00
cfed96a410
fix breakage from r98938 by correctly marking msp430 calls as variadic.
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Patch by Ben Ransford!
llvm-svn: 106722
2010-06-24 06:46:50 +00:00
c3e291c560
Fix a bug in the code which determines when it's safe to use the
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bt instruction, which was exposed by r106263.
llvm-svn: 106718
2010-06-24 02:07:59 +00:00
fa6ce139a9
Add a couple more quick comments.
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llvm-svn: 106717
2010-06-24 02:07:57 +00:00
0dc3c2d37e
Use ValueMap instead of DenseMap.
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The ValueMapper used by various cloning utility maps MDNodes also.
llvm-svn: 106706
2010-06-24 00:33:28 +00:00
191a1cd2bb
Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases
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llvm-svn: 106705
2010-06-24 00:32:06 +00:00
6af02a6f69
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
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llvm-svn: 106702
2010-06-24 00:15:50 +00:00
f470747a36
We are missing opportunites to use ldm. Take code like this:
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void t(int *cp0, int *cp1, int *dp, int fmd) {
int c0, c1, d0, d1, d2, d3;
c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
/* ... */
}
It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.
llvm-svn: 106693
2010-06-23 23:00:16 +00:00
05220c9a0d
Add AVX MOVMSK{PS,PD}rr instructions
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llvm-svn: 106683
2010-06-23 21:30:27 +00:00
3183dd5692
Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction
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llvm-svn: 106678
2010-06-23 21:10:57 +00:00
Gabor Greif