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Author SHA1 Message Date
Owen Anderson f902d92fc9 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
llvm-svn: 140079
 2011-09-19 22:34:23 +00:00
Jim Grosbach 05541f45f3 Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Jim Grosbach 1a23fbb9fd Tidy up a bit. 
llvm-svn: 140050
 2011-09-19 20:31:59 +00:00
Jim Grosbach 8221319707 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Owen Anderson 8c021d85a6 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. 
llvm-svn: 140041
 2011-09-19 20:00:02 +00:00
Jim Grosbach 40700e0992 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035
 2011-09-19 18:42:21 +00:00
Owen Anderson ddfcec92d9 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Jim Grosbach 264abdecf0 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
llvm-svn: 140029
 2011-09-19 17:56:37 +00:00
Owen Anderson 502cd9d87a Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
llvm-svn: 139972
 2011-09-16 23:30:01 +00:00
Owen Anderson b925e935d7 Fix bitfield decoding based on Eli's feedback. 
llvm-svn: 139969
 2011-09-16 23:04:48 +00:00
Jim Grosbach d0c435c23c Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Owen Anderson bcfa9a6f89 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
llvm-svn: 139965
 2011-09-16 22:42:36 +00:00
Owen Anderson 3ca958cd19 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Owen Anderson 9764bced10 Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
llvm-svn: 139958
 2011-09-16 22:17:02 +00:00
Jim Grosbach 9c0b86a76d Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949
 2011-09-16 21:55:56 +00:00
Jim Grosbach 5c3657a0e5 Tidy up. 80 columns. 
llvm-svn: 139944
 2011-09-16 21:09:00 +00:00
Owen Anderson fe82365cb0 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00
Jim Grosbach 92606beeae Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

llvm-svn: 139942
 2011-09-16 21:06:12 +00:00
Jim Grosbach 099c9767c3 Thumb2 assembly parsing and encoding for STMIA. 
llvm-svn: 139938
 2011-09-16 20:50:13 +00:00
Jim Grosbach 8aee874bf1 Thumb2 assembly parsing and encoding for SSAX. 
llvm-svn: 139929
 2011-09-16 18:37:10 +00:00
Jim Grosbach 9d9c99ff07 Thumb2 assembly parsing and encoding for SSAT. 
llvm-svn: 139926
 2011-09-16 18:32:30 +00:00
Jim Grosbach e6e7cd146a Thumb2 assembly parsing and encoding for SRS. 
llvm-svn: 139925
 2011-09-16 18:25:22 +00:00
Jim Grosbach d73c6458de Thumb2 assembly parsing and encoding for SMMULL. 
llvm-svn: 139921
 2011-09-16 18:05:48 +00:00
Jim Grosbach c1826a9de0 Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
llvm-svn: 139909
 2011-09-16 17:10:44 +00:00
Jim Grosbach 7a0b90b187 Thumb2 assembly parsing and encoding for SMLALD/SMLALDX. 
llvm-svn: 139906
 2011-09-16 16:58:03 +00:00
Jim Grosbach 5e6d5cd7da Kill some dead code. 
llvm-svn: 139904
 2011-09-16 16:45:40 +00:00
Jim Grosbach 6c45b75154 Tidy up a bit. 
llvm-svn: 139903
 2011-09-16 16:39:25 +00:00
Jim Grosbach f9799d2c2d Thumb2 assembly parsing and encoding for SMLAL. 
llvm-svn: 139902
 2011-09-16 16:38:00 +00:00
Jim Grosbach 10a93ff8e0 Remove incorrect comments. 
llvm-svn: 139877
 2011-09-15 23:45:50 +00:00
Owen Anderson a0c3b97221 Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
llvm-svn: 139876
 2011-09-15 23:38:46 +00:00
Jim Grosbach b08ce9b4c4 Thumb2 assembly parsing and encoding for SHASX/SHSAX. 
llvm-svn: 139870
 2011-09-15 22:34:29 +00:00
Eli Friedman 10f9ce2b7d Minor cleanup. 
llvm-svn: 139869
 2011-09-15 22:26:18 +00:00
Eli Friedman ba912e06c2 Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1. 
llvm-svn: 139865
 2011-09-15 22:18:49 +00:00
Jim Grosbach 10725a202b Thumb2 assembly parsing and encoding for SASX. 
llvm-svn: 139843
 2011-09-15 21:01:23 +00:00
Jim Grosbach eaa5265285 Thumb2 assembly parsing and encoding for RSB. 
llvm-svn: 139839
 2011-09-15 20:54:14 +00:00
Jim Grosbach 4cbe06e7f8 Thumb2 assembly parsing and encoding for REV16/REVSH. 
llvm-svn: 139828
 2011-09-15 19:46:13 +00:00
Owen Anderson d1814791ad Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. 
llvm-svn: 139820
 2011-09-15 18:36:29 +00:00
Jim Grosbach ab154f0b65 Thumb2 assembly parsing and encoding for REV. 
llvm-svn: 139813
 2011-09-15 18:13:30 +00:00
Jim Grosbach d93c4ece15 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' 
llvm-svn: 139796
 2011-09-15 16:16:50 +00:00
Jim Grosbach 22f76390a6 Thumb2 push/pop mnemonic recognition. 
llvm-svn: 139794
 2011-09-15 15:55:04 +00:00
Jim Grosbach 801e06b768 Thumb2 assembly parsing and encoding for PKH. 
llvm-svn: 139754
 2011-09-14 23:16:41 +00:00
Jim Grosbach 521526845c ARMv7a has the PKH instructions. 
llvm-svn: 139753
 2011-09-14 23:16:34 +00:00
Jim Grosbach 25ca53b268 ARM tighten up the register classes for the PKH instructions. 
llvm-svn: 139748
 2011-09-14 22:52:14 +00:00
Owen Anderson d7791b961c Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
llvm-svn: 139747
 2011-09-14 22:46:14 +00:00
Jim Grosbach 752d6fd529 Thumb2 assembly parsing and encoding for MVN. 
llvm-svn: 139739
 2011-09-14 21:24:41 +00:00
Owen Anderson f1e384421a Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
llvm-svn: 139736
 2011-09-14 21:06:21 +00:00
Jim Grosbach 9c8b9932d6 Thumb2 assembly parsing and encoding for MUL. 
llvm-svn: 139735
 2011-09-14 21:00:40 +00:00
Jim Grosbach 0ecd395095 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

llvm-svn: 139721
 2011-09-14 20:03:46 +00:00
Jim Grosbach 18b8b17579 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

llvm-svn: 139714
 2011-09-14 19:12:11 +00:00
Jim Grosbach 3ac26b138b ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573

llvm-svn: 139707
 2011-09-14 18:08:35 +00:00
Jim Grosbach 75461af000 Remove unnecessary scope resolution operator. 
llvm-svn: 139656
 2011-09-13 22:56:44 +00:00
Owen Anderson 7f0e98fd7f Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
llvm-svn: 139639
 2011-09-13 20:46:26 +00:00
Jim Grosbach e3a6a82f16 There's only 16 regs legal in a register list. 
llvm-svn: 139637
 2011-09-13 20:35:57 +00:00
Jim Grosbach e7e2aca322 Tidy up a few 80 column violations. 
llvm-svn: 139636
 2011-09-13 20:30:37 +00:00
Jim Grosbach 50087ea1ec Tidy up a bit. 
llvm-svn: 139635
 2011-09-13 20:27:44 +00:00
Owen Anderson 44ae2da4ec Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
llvm-svn: 139610
 2011-09-13 17:59:19 +00:00
Owen Anderson c3c60a0882 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
llvm-svn: 139606
 2011-09-13 17:34:32 +00:00
Eli Friedman 12ea1b72a4 Zap some junk from the ARM instruction descriptions. 
llvm-svn: 139575
 2011-09-13 02:29:58 +00:00
Jim Grosbach 3337e396c8 Tidy up a bit. 
llvm-svn: 139559
 2011-09-12 23:36:42 +00:00
Owen Anderson 2a206c44b7 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
llvm-svn: 139542
 2011-09-12 21:28:46 +00:00
Owen Anderson 4a9eb5f8dc Fix encoding of PC-relative LDRSHW with an immediate offset. 
llvm-svn: 139537
 2011-09-12 20:36:51 +00:00
Owen Anderson 3543398bcf There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> 
llvm-svn: 139531
 2011-09-12 20:07:22 +00:00
Owen Anderson a9ebf6fb64 Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
llvm-svn: 139522
 2011-09-12 18:56:30 +00:00
Jim Grosbach b908b7af31 Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440
 2011-09-10 00:15:36 +00:00
Owen Anderson 53db43b560 LDM writeback is not allowed if Rn is in the target register list. 
llvm-svn: 139432
 2011-09-09 23:13:33 +00:00
Owen Anderson eb3f0fbdce Fix an ambiguously nested if. 
llvm-svn: 139431
 2011-09-09 23:13:02 +00:00
Owen Anderson 93cd31869b Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB. 
llvm-svn: 139429
 2011-09-09 23:05:14 +00:00
Owen Anderson 5bfb0e0a85 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Jim Grosbach 62c33955e2 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Jim Grosbach 779a2bee7b Thumb2 assembly parsing and encoding for LDRSB. 
llvm-svn: 139389
 2011-09-09 19:42:40 +00:00
Jim Grosbach a05627ebaf Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Owen Anderson 33d39536e6 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
llvm-svn: 139329
 2011-09-08 22:48:37 +00:00
Owen Anderson 2fefa427d5 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
llvm-svn: 139328
 2011-09-08 22:42:49 +00:00
Jim Grosbach 7db8d697cf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Jim Grosbach 3343da5424 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272
 2011-09-08 01:01:32 +00:00
Jim Grosbach c086f689f8 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Owen Anderson f174959286 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
llvm-svn: 139268
 2011-09-08 00:11:18 +00:00
Jim Grosbach 2392c53e73 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach e0ebc1c396 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Jim Grosbach c8e3656b43 Thumb2 assembly parsing and encoding for LDRB(immediate). 
llvm-svn: 139258
 2011-09-07 21:41:25 +00:00
Owen Anderson 18d17aa6b7 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
Jim Grosbach 5bfa8bab06 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
 2011-09-07 20:58:57 +00:00
Jim Grosbach 1c7406767e Thumb2 parsing and encoding for LDMDB. 
llvm-svn: 139251
 2011-09-07 19:57:53 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Jim Grosbach 42b5570850 Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix. 
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

llvm-svn: 139243
 2011-09-07 18:39:47 +00:00
Jim Grosbach a31f223af8 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Owen Anderson cd5612d3a5 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
llvm-svn: 139240
 2011-09-07 17:55:19 +00:00
James Molloy 4c493e8050 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
llvm-svn: 139237
 2011-09-07 17:24:38 +00:00
Jim Grosbach 4ff93f3bc2 Thumb2 use 'ldm' as default mnemonic. 
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

llvm-svn: 139234
 2011-09-07 16:22:42 +00:00
Jim Grosbach 39c6e1d66d Better diagnostic location information for mnemonic suffices. 
llvm-svn: 139232
 2011-09-07 16:06:04 +00:00
Jim Grosbach 5b5c953b07 ISB is HasDB, not just HasV7. 
llvm-svn: 139202
 2011-09-06 23:09:19 +00:00
Jim Grosbach 83a6188f18 Thumb2 parsing and encoding for ISB. 
llvm-svn: 139200
 2011-09-06 22:53:27 +00:00
Jim Grosbach e95f46384e Thumb2 parsing and encoding for DMB. 
llvm-svn: 139193
 2011-09-06 22:14:58 +00:00
Jim Grosbach c048b905b4 Thumb2 parsing and encoding for DBG. 
llvm-svn: 139191
 2011-09-06 22:06:40 +00:00
Jim Grosbach 565e2f5752 Thumb2 parsing and encoding for CMN and CMP. 
llvm-svn: 139188
 2011-09-06 21:44:58 +00:00
Eli Friedman fc4b343dda Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions. 
llvm-svn: 139179
 2011-09-06 20:53:37 +00:00
Jim Grosbach 803898f119 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Duncan Sands f2641e1bc1 Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Evan Cheng 0b758ed6ba Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
 2011-09-06 18:52:20 +00:00
Jim Grosbach f471ac3c72 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155
 2011-09-06 18:46:23 +00:00
Jakob Stoklund Olesen 50ef7611aa Atomic pseudos don't use (as in read) CPSR. They clobber it. 
llvm-svn: 139148
 2011-09-06 17:40:35 +00:00
Nick Lewycky 73df7e3830 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
 2011-09-05 21:51:43 +00:00
Nick Lewycky f1a5f57d2f Fix typo in comment. 
llvm-svn: 139122
 2011-09-05 18:35:03 +00:00
Jim Grosbach 34842ceb97 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach a216debb37 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Jim Grosbach 05dec8b122 Tidy up. Formatting. 
llvm-svn: 139024
 2011-09-02 18:46:15 +00:00
Jim Grosbach 0a57375a28 Tidy up. 80 columns. 
llvm-svn: 139022
 2011-09-02 18:43:25 +00:00
Jim Grosbach 370e923434 Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jim Grosbach 2761155203 Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Owen Anderson ed96b58bd2 Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson 03aadae01f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman d7776ed030 Null-initialize to shut up -Wuninitialized warnings. 
llvm-svn: 138974
 2011-09-01 22:27:41 +00:00
Jim Grosbach f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
James Molloy db4ce60328 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson 35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Chad Rosier 17847ae757 Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach e1995f2566 Static relocation model Thumb jump table interworking. 
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
 2011-08-31 22:23:09 +00:00
Owen Anderson 4af0aa98d5 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
Jim Grosbach 99bc84662f Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Owen Anderson a455a0b1e7 Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Owen Anderson 939cd21248 When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. 
<rdar://problem/10046188>

llvm-svn: 138885
 2011-08-31 20:00:11 +00:00
Jim Grosbach cfa9421e16 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Owen Anderson 5c160fd243 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Jim Grosbach c61fc8f301 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Jim Grosbach af8c3cc710 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Eli Friedman 1ccecbb9d3 64-bit atomic cmpxchg for ARM. 
llvm-svn: 138868
 2011-08-31 17:52:22 +00:00
Jim Grosbach 6d606fbe14 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jakob Stoklund Olesen cd893390f5 Put VMOVS widening under a command line option, off by default. 
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861
 2011-08-31 17:00:02 +00:00
Eli Friedman 2c7bb52f56 Some minor cleanups for r138845. 
llvm-svn: 138846
 2011-08-31 00:41:05 +00:00
Eli Friedman c3f9c4a852 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
llvm-svn: 138845
 2011-08-31 00:31:29 +00:00
Owen Anderson 2fa06a7226 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson fdf3cd7f2b Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Owen Anderson d16fb43b1f Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson 543c89fb15 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Owen Anderson 1732c2ebf6 Clean up whitespace. 
llvm-svn: 138833
 2011-08-30 21:58:18 +00:00
Evan Cheng e6fba77971 Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
 2011-08-30 19:09:48 +00:00
Evan Cheng e891654a58 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791
 2011-08-30 01:34:54 +00:00
Jim Grosbach 6e59d5c916 Revert 138781. It's not playing nicely with the immediate forms for ADC. 
llvm-svn: 138782
 2011-08-29 23:24:15 +00:00
Jim Grosbach 19a75f075d Thumb2 assembler aliases for ADC/SBC w/o the .w suffix. 
llvm-svn: 138781
 2011-08-29 23:20:54 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Owen Anderson 243274c789 Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. 
llvm-svn: 138766
 2011-08-29 21:14:19 +00:00
Owen Anderson 32ac76616e Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding. 
llvm-svn: 138760
 2011-08-29 20:42:00 +00:00
Owen Anderson 4d5c8f894d addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. 
llvm-svn: 138758
 2011-08-29 20:16:50 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Eli Friedman 7dfa791f4f Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Owen Anderson 6314343333 Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653. 
llvm-svn: 138746
 2011-08-29 17:59:41 +00:00
Owen Anderson f02d98d7c0 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Benjamin Kramer 61a1ff543c Silence GCC warnings and make an array const. 
llvm-svn: 138706
 2011-08-27 17:36:14 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson 6c70e58041 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00
Jim Grosbach b9d4e37776 ARM assembly parsing tweak for pldw. 
llvm-svn: 138669
 2011-08-26 22:21:51 +00:00
Owen Anderson 240d20af79 Spelling fail. 
llvm-svn: 138667
 2011-08-26 21:47:57 +00:00
Jim Grosbach 3d1eac85c3 Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.

llvm-svn: 138665
 2011-08-26 21:43:41 +00:00
Owen Anderson fd60f60ed1 Fix ARM codegen breakage caused by r138653. 
llvm-svn: 138657
 2011-08-26 21:12:37 +00:00
Owen Anderson 16d33f36d5 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Owen Anderson 5658b49f64 Update for feedback from Jim. 
llvm-svn: 138642
 2011-08-26 19:39:26 +00:00
Benjamin Kramer aa38dbadca ARMDisassembler: Always return a size, even when disassembling fails. 
This should fix PR10772.

llvm-svn: 138636
 2011-08-26 18:21:36 +00:00
Owen Anderson a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Owen Anderson 149695627a Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors. 
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625
 2011-08-26 06:19:51 +00:00
Eli Friedman 452aae6202 Atomic load/store on ARM/Thumb. 
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621
 2011-08-26 02:59:24 +00:00
Nick Lewycky 64bfca1b60 Remove stray fullstop. 
llvm-svn: 138589
 2011-08-25 21:46:20 +00:00
Owen Anderson 5e30972cff Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
llvm-svn: 138575
 2011-08-25 18:30:18 +00:00
Andrew Trick 6446bf780a ARM fix for missing implicit operands on ldmia_ret. 
rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568
 2011-08-25 17:50:53 +00:00
Andrew Trick f7ecc16c96 whitespace 
llvm-svn: 138566
 2011-08-25 17:40:54 +00:00
Jim Grosbach 1c171b121a Explicitly disallow predication in Thumb1 assembly. 
llvm-svn: 138562
 2011-08-25 17:23:55 +00:00
Evan Cheng 9dad430486 Hide -global-merge option. 
llvm-svn: 138540
 2011-08-25 01:22:49 +00:00
Evan Cheng f066b2fe99 Add a command line option to disable global merge pass. 
llvm-svn: 138536
 2011-08-25 01:00:36 +00:00
Evan Cheng 3ca20e64ac Remove a out-of-place comment. 
llvm-svn: 138534
 2011-08-25 00:54:42 +00:00
Owen Anderson 37612a3de3 Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space. 
llvm-svn: 138507
 2011-08-24 22:40:22 +00:00
Jim Grosbach 21a60b6f90 ARM asm backend initialize isThumbMode based on target triple. 
llvm-svn: 138501
 2011-08-24 22:27:35 +00:00
Jim Grosbach 838ed3af46 Thumb .n mnemonic qualifiers can be ignored for now. 
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

llvm-svn: 138500
 2011-08-24 22:19:48 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
 2011-08-24 21:42:27 +00:00
Owen Anderson 216cfaa808 Be careful not to walk off the end of the operand info list while updating VFP predicates. 
llvm-svn: 138492
 2011-08-24 21:35:46 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Jim Grosbach af2f827a2c When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate. 
rdar://10015134

llvm-svn: 138467
 2011-08-24 20:06:14 +00:00
Jim Grosbach 6ccd79f4d5 Add missing explicit writeback operand to tSTMIA_UPD. 
rdar://10014745

llvm-svn: 138457
 2011-08-24 18:19:42 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Jim Grosbach a281f2d07d Thumb add SP assembly syntax fix. 
llvm-svn: 138448
 2011-08-24 18:04:27 +00:00
Jim Grosbach 1b8457a84c Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. 
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445
 2011-08-24 17:46:13 +00:00
Owen Anderson 523004145e Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate. 
llvm-svn: 138443
 2011-08-24 17:21:43 +00:00
Jim Grosbach 51b554247d Move ARM frame-unwinding EHABI handling a touch earlier. 
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

llvm-svn: 138386
 2011-08-23 21:32:34 +00:00
Jim Grosbach 50b0f6669c [SU]XT[BH] are only available on ARMv6 and up. 
llvm-svn: 138373
 2011-08-23 20:53:08 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.

llvm-svn: 138367
 2011-08-23 20:15:21 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC. 
llvm-svn: 138360
 2011-08-23 19:49:10 +00:00
Jim Grosbach 505be75900 Thumb parsing and encoding for tSTRspi. 
llvm-svn: 138348
 2011-08-23 18:39:41 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Jim Grosbach 169b2be611 Factor low reg checking into a helper function. 
llvm-svn: 138344
 2011-08-23 18:13:04 +00:00
Owen Anderson 924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Owen Anderson 9b7bd15d0b Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions. 
llvm-svn: 138339
 2011-08-23 17:45:18 +00:00
Jim Grosbach e364ad540a Clean up Thumb load/store multiple definitions. 
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338
 2011-08-23 17:41:15 +00:00
Owen Anderson 041dba6dec Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
llvm-svn: 138337
 2011-08-23 17:37:32 +00:00
Jim Grosbach 3636be3c8f Thumb parsing and encoding for SBC. 
llvm-svn: 138311
 2011-08-22 23:55:58 +00:00
Jim Grosbach c3c32d9e09 Thumb parsing and encoding for RSB. 
llvm-svn: 138308
 2011-08-22 23:47:13 +00:00
Owen Anderson eb1367b2b8 Reject invalid imod values in t2CPS instructions. 
llvm-svn: 138306
 2011-08-22 23:44:04 +00:00
Owen Anderson 1346d79b4b t2SMLAD is a four-register instruction, not a three-register one. 
llvm-svn: 138301
 2011-08-22 23:31:45 +00:00
Owen Anderson f94b7b7d57 Correct operand naming of t2USAT16 to allow proper decoding. 
llvm-svn: 138300
 2011-08-22 23:27:47 +00:00
Jim Grosbach bfeb4f78af Revert r138278 now that r138289 has fixed the root issue. 
llvm-svn: 138299
 2011-08-22 23:25:48 +00:00
Owen Anderson 5e9989a920 Match operand naming to allow correct decoding of t2LDRSH_POST. 
llvm-svn: 138298
 2011-08-22 23:22:05 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Owen Anderson 2844a81079 Match operand names to provide correct decoding for Thumb2 SMULL. 
llvm-svn: 138294
 2011-08-22 23:16:48 +00:00
Owen Anderson a743409ec8 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
llvm-svn: 138292
 2011-08-22 23:10:16 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Jim Grosbach ca2ffad8b1 Temporarilly mark tMUL as not commutable. 
It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.

llvm-svn: 138278
 2011-08-22 22:00:18 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
llvm-svn: 138273
 2011-08-22 21:34:00 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00
Jim Grosbach 5c932b24be Tighten up ARM reglist validation a bit. 
llvm-svn: 138258
 2011-08-22 18:50:36 +00:00
Owen Anderson 721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Owen Anderson ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Jim Grosbach 6caa557ae6 Clean up predicates on ARM target instruction aliases. 
llvm-svn: 138249
 2011-08-22 18:04:24 +00:00
Owen Anderson b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Chad Rosier 61f92efb5c Remove the VMOVQQ pseudo instruction. 
llvm-svn: 138177
 2011-08-20 00:52:40 +00:00
Chad Rosier baf5538da9 Remove VMOVQQQQ pseudo instruction. 
llvm-svn: 138174
 2011-08-20 00:40:14 +00:00
Jakob Stoklund Olesen 59015c8b17 Add <imp-def> operands to QQ and QQQQ stack loads. 
This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

llvm-svn: 138164
 2011-08-20 00:17:45 +00:00
Chad Rosier be7625161e VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
 2011-08-20 00:17:25 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach 8022015a16 Fix NEG alias 
llvm-svn: 138125
 2011-08-19 22:30:58 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Jim Grosbach 066e9ec1e4 Update tests. 
llvm-svn: 138116
 2011-08-19 22:19:48 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach dbb60f960a Tidy up. Tab character. 
llvm-svn: 138072
 2011-08-19 20:30:19 +00:00
Jim Grosbach 9c92049069 Tab characters. 
llvm-svn: 138066
 2011-08-19 19:41:46 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach 7473329725 Use helper function to check for low registers. 
llvm-svn: 138048
 2011-08-19 17:57:22 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Jim Grosbach e93807049b Add explanatory comment. 
llvm-svn: 138042
 2011-08-19 16:52:32 +00:00
Benjamin Kramer 4938edb02c Make a bunch of symbols private. 
llvm-svn: 138025
 2011-08-19 01:42:18 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson 5d2db89ba6 Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails. 
llvm-svn: 137997
 2011-08-18 22:15:25 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
Jim Grosbach 8a6bed863a Thumb instructions CBZ and CBNZ are Thumb2, not THumb1. 
llvm-svn: 137956
 2011-08-18 17:51:36 +00:00
Jim Grosbach f00b9ccd22 ARM Thumb blx instruction fixup has same data range as bl. 
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
 2011-08-18 16:57:50 +00:00
Jim Grosbach 8fa3f6a2b4 80 columns. 
llvm-svn: 137946
 2011-08-18 16:50:45 +00:00
Jim Grosbach 6ddb568ab8 Add missing 'break'. 
llvm-svn: 137941
 2011-08-18 16:08:39 +00:00
Jim Grosbach 50aafeaa2c Remove extraneous newline from operand print method. PR10569. 
llvm-svn: 137900
 2011-08-17 23:23:07 +00:00