Commit Graph

81 Commits

Author SHA1 Message Date
Dan Gohman fc4ad7de66 Move instruction flag inference out of InstrInfoEmitter and into
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags. 

This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.

llvm-svn: 49123
2008-04-03 00:02:49 +00:00
Chris Lattner ab3242fd46 rename CodegenDAGPatterns -> CodeGenDAGPatterns
llvm-svn: 45641
2008-01-06 01:10:31 +00:00
Chris Lattner 7980bba549 now that computing CodegenDAGPatterns doesn't implicitly print stuff
out, DAGISelEmitter can compute it in its ctor, which simplifies some code.

Now we can use CodegenDAGPatterns in other parts of tblgen that want access
to dag pattern info, woo!

llvm-svn: 45636
2008-01-05 22:58:54 +00:00
Chris Lattner cc43e79bcd move Node Transformation printing from CodeGenDAGPatterns -> DAGISelEmitter.
The only difference in output is that we now print them in alphabetical 
order instead of reverse alphabetical order.

llvm-svn: 45635
2008-01-05 22:54:53 +00:00
Chris Lattner e7170df043 move predicate printing code from CodeGenDAGPatterns -> DAGISelEmitter.
llvm-svn: 45634
2008-01-05 22:43:57 +00:00
Chris Lattner 9abe77b2d0 fix a fixme by improving const correctness.
llvm-svn: 45633
2008-01-05 22:30:17 +00:00
Chris Lattner 8cab021ca2 change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.

llvm-svn: 45632
2008-01-05 22:25:12 +00:00
Chris Lattner 8adcd9f32e remove attributions from utils.
llvm-svn: 45419
2007-12-29 20:37:13 +00:00
Evan Cheng 59c39dc197 Initial support for multi-result patterns:
1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897
2007-09-12 23:30:14 +00:00
Evan Cheng a7d41aad4f Refactor code to add initial support for OptionalDefOperand.
llvm-svn: 37933
2007-07-06 01:05:26 +00:00
Chris Lattner ed07f23c52 Parse PredicateOperand's. When an instruction takes one, have the generated
isel fill in the instruction operands with the 'execute always' value
automatically.

llvm-svn: 31448
2006-11-04 05:12:02 +00:00
Evan Cheng 2022c79d7f Added properties such as SDNPHasChain to ComplexPattern.
llvm-svn: 30890
2006-10-11 21:02:01 +00:00
Evan Cheng eaf9fba2ff A bit more clean up.
llvm-svn: 29893
2006-08-26 01:02:19 +00:00
Evan Cheng 548bd0dc95 - Clean up tablegen dag isel generator code.
- Clean up the code generated by tablegen:
  * AddToISelQueue now takes one argument.
  * ComplexPattern matching condition can now be shared.
  * Eliminate passing unnecessary arguments to emit routines.
  * Eliminate some unneeded SDOperand declarations in select routines.
  * Other minor clean ups.
- This reduces foot print slightly: X86ISelDAGToDAG.o is reduced from 971k
  to 823k.

llvm-svn: 29892
2006-08-26 00:59:04 +00:00
Evan Cheng 97d5cc165a Making TableGen'd instruction selection code non-recursive. This fixes PR805.
llvm-svn: 29548
2006-08-07 22:17:58 +00:00
Evan Cheng 87b2fe9474 Parameterize target node ValueType to allow more sharing of emit functions.
Also reduce the number of arguments passed to emit functions and removed a
hack.

llvm-svn: 29160
2006-07-16 06:12:52 +00:00
Evan Cheng 69367fedd2 Reduce instruction selection code size and stack frame size by factoring
code that emit target specific nodes into emit functions that are uniquified
and shared among selection routines.
e.g. This reduces X86ISelDAGToDAG.o (release) from ~2M to ~1.5M. Stack frame
size of Select_store from ~13k down to ~8k.
This is the first step. Further work to enable more sharing will follow.

llvm-svn: 29158
2006-07-15 08:45:20 +00:00
Evan Cheng f5ef47fe74 Remove PointerType from target definition. Use abstract type MVT::iPTR to
represent pointer type.

llvm-svn: 28363
2006-05-17 20:37:59 +00:00
Evan Cheng 9235d848b7 Rename AddedCost to AddedComplexity.
llvm-svn: 27841
2006-04-19 20:36:09 +00:00
Evan Cheng aa3325e925 Allow "let AddedCost = n in" to increase pattern complexity.
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
Chris Lattner c8565ed651 Change approach so that we get codegen for free for intrinsics. With this,
intrinsics that don't take pointer arguments now work.  For example, we can
compile this:

int test3( __m128d *A) {
  return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
  return _mm_movemask_ps(*A);
}

to this:

_test3:
        movl 4(%esp), %eax
        movapd (%eax), %xmm0
        movmskpd %xmm0, %eax
        ret
_test4:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        movmskps %xmm0, %eax
        ret

llvm-svn: 27090
2006-03-24 23:10:39 +00:00
Chris Lattner e352e7aa85 Parse intrinsics correctly and perform type propagation. This doesn't currently
emit the code to select intrinsics, but that is next :)

llvm-svn: 27082
2006-03-24 21:48:51 +00:00
Evan Cheng a84bdebfd2 Copy matching pattern's output type info to instruction result pattern.
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.

llvm-svn: 26892
2006-03-20 06:04:09 +00:00
Chris Lattner c1b31d8a83 Add a new SDTCisIntVectorOfSameSize type constraint
llvm-svn: 26890
2006-03-20 05:39:48 +00:00
Evan Cheng 9ce762d51f Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
Evan Cheng 1630c2848f Hoist all SDOperand declarations within a Select_{opcode}() to the top level
to reduce stack memory usage. This is intended to work around the gcc bug.

llvm-svn: 26026
2006-02-07 00:37:41 +00:00
Evan Cheng 368f20e53d Allow more loads to be folded which were previously prevented from happening
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.

llvm-svn: 25995
2006-02-05 06:43:12 +00:00
Chris Lattner 7c0149d1d6 Factor matching code that is common between patterns. This works around
GCC not jump-threading across this common code, and produces far nicer
output.

llvm-svn: 25762
2006-01-29 04:25:26 +00:00
Chris Lattner afe9baeb69 move some code around, no change in the generated code
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
Jeff Cohen e251e92c23 Teach tablegen to generate code that is VC++ warning-free.
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
Chris Lattner dce31c8d70 fix a broken comment
llvm-svn: 25411
2006-01-17 21:31:18 +00:00
Evan Cheng 4b0623e141 * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.

llvm-svn: 25154
2006-01-09 18:27:06 +00:00
Nate Begeman 336dba6fb1 Add support for generating v4i32 altivec code
llvm-svn: 25046
2005-12-30 00:12:56 +00:00
Evan Cheng 72aaf8e374 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
support which is fragile.
* Fixed a number of bugs.

llvm-svn: 24996
2005-12-23 22:11:47 +00:00
Evan Cheng 991bc6d6ba * Added support for FLAG - a special nameless flag register. Can be used as
either an operand or a result.
* Fixed some more flag / chain bugs.

llvm-svn: 24933
2005-12-22 02:24:50 +00:00
Evan Cheng e22f9181f7 Support for read / write from explicit registers with FlagVT type.
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
Evan Cheng d296a43f96 Added support to specify predicates.
llvm-svn: 24715
2005-12-14 22:02:59 +00:00
Chris Lattner 433573f4c6 Add a new SDTCisPtrTy constraint, which indicates that an operand must have
the same type as the pointer type for a target.

llvm-svn: 24649
2005-12-09 22:57:42 +00:00
Evan Cheng 499ab2a9fa * Do not allow nodes which produce chain results (e.g. loads) to be folded if
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
  operand of a chain use.

llvm-svn: 24647
2005-12-09 22:45:35 +00:00
Evan Cheng c1f911a238 Prevent folding of instructions which produce chains that have more than 1 real use
llvm-svn: 24643
2005-12-09 06:06:08 +00:00
Evan Cheng f423a17e33 * Make sure complex pattern operands are selected first since their select
functions can return false and causing the instruction pattern match to fail.
* Code clean up.

llvm-svn: 24642
2005-12-09 00:48:42 +00:00
Evan Cheng 9b9567bfb5 Added support for ComplexPattern. These are patterns that require C++ pattern
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.

llvm-svn: 24634
2005-12-08 02:00:36 +00:00
Evan Cheng f02bb9af8b * Commit the fix (by Chris) for a tblgen type inferencing bug.
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
2005-12-04 08:18:16 +00:00
Evan Cheng fed83adbe3 Teach tblgen to accept register source operands in patterns, e.g.
def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.

llvm-svn: 24557
2005-12-01 00:18:45 +00:00
Nate Begeman cdf2c67888 Stop checking the ValueType of the CodeGenInstruction. Instead, use the
ValueType from the RegisterClass or Operands.  This step is necessary to
allow RegisterClasses to have multiple ValueTypes.

llvm-svn: 24555
2005-12-01 00:06:14 +00:00
Chris Lattner 590176be16 Add support for immediates directly in the pattern, this allows itanium to
define:

def : Pat<(i1 1), (CMPEQ r0, r0)>;

llvm-svn: 24149
2005-11-02 06:49:14 +00:00
Chris Lattner 8bda5afd91 Make tblgen emit:
tblgen: In ZAPNOTi: Cannot use 'IZAPX' in an input pattern!
for a bad pattern, instead of an ugly assertion.

llvm-svn: 23854
2005-10-21 01:19:59 +00:00
Chris Lattner 2ae2f99326 Fix some checking that was causing duraid to get a perplexing assertion
instead of a happy error message

llvm-svn: 23816
2005-10-19 04:12:14 +00:00
Chris Lattner 825298b060 Make the generated code significantly more memory efficient, by using
SelectNodeTo instead of getTargetNode when possible.

llvm-svn: 23758
2005-10-16 01:41:58 +00:00
Chris Lattner ecaf56b21a Fairly serious rework of the typing code to add new int/fp lattice values.
Overall, no functionality change yet though.

llvm-svn: 23729
2005-10-14 06:12:03 +00:00