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5 Commits

Author SHA1 Message Date
Matt Arsenault 663ab8c119 AMDGPU: Use brev for materializing SGPR constants 
This is already done with VGPR immediates and saves 4 bytes.

llvm-svn: 285765
 2016-11-01 23:14:20 +00:00
Matt Arsenault bbb47da8a1 AMDGPU: Support commuting with immediate in src0 
llvm-svn: 280970
 2016-09-08 17:19:29 +00:00
Tom Stellard cb6ba62d6f AMDGPU/SI: Enable the post-ra scheduler 
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.

Reviewers: arsenm

Subscribers: qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18602

llvm-svn: 268143
 2016-04-30 00:23:06 +00:00
Tom Stellard e48fe2a27a AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions 
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11061

llvm-svn: 242146
 2015-07-14 14:15:03 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00