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2 Commits

Author SHA1 Message Date
Jan Vesely e8cc395e4f AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument 
wbinvl.* are vector instruction that do not sue vector registers.

v2: check only M?BUF instructions

Differential Revision: https://reviews.llvm.org/D26633

llvm-svn: 287056
 2016-11-15 23:55:15 +00:00
Matt Arsenault d6adfb401c AMDGPU: Add cache invalidation instructions. 
These are necessary for implementing mem_fence for
OpenCL 2.0.

The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.

llvm-svn: 248532
 2015-09-24 19:52:21 +00:00