Commit Graph

171410 Commits

Author SHA1 Message Date
Rafael Espindola c498415086 Reuse existing variable.
llvm-svn: 205572
2014-04-03 21:48:41 +00:00
Eli Bendersky bbef172f19 Optimize away unnecessary address casts.
Removes unnecessary casts from non-generic address spaces to the generic address
space for certain code patterns.

Patch by Jingyue Wu.

llvm-svn: 205571
2014-04-03 21:18:25 +00:00
Rui Ueyama 517f0d9b5f Minor cleanup.
llvm-svn: 205570
2014-04-03 21:16:37 +00:00
Rui Ueyama 83e6acc7f2 Simplify two if's.
llvm-svn: 205569
2014-04-03 21:11:22 +00:00
Rui Ueyama fb44f5e278 Fix comments.
llvm-svn: 205568
2014-04-03 21:06:23 +00:00
Rui Ueyama 6aa91cf13d Early return.
llvm-svn: 205567
2014-04-03 21:00:03 +00:00
Rui Ueyama 9457510abf Fix ELFFileNode::resetNextIndex().
ELFLinkingContext has a method addUndefinedAtomsFromSharedLibrary().
The method is being used to skip a shared library within --start-group
and --end-group if it's not the first iteration of the group.

We have the same, incomplete mechanism to skip a shared library within
a group too. That's implemented in ELFFileNode. It's intended to not
return a shared library on the second or further iterations in the
first place. This mechanism is preferred over
addUndefinedAtomsFromSharedLibrary because the policy is implemented
in Input Graph -- that's what Input Graph is for.

This patch removes the dupluicate feature and fixes ELFFileNode.

Differential Revision: http://llvm-reviews.chandlerc.com/D3280

llvm-svn: 205566
2014-04-03 20:54:47 +00:00
Lang Hames cb74fa696b [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.
When rematerializing through truncates, the coalescer may produce instructions
with dead defs, but live implicit-defs of subregs:
E.g.
  %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32

These instructions are live, and their definitions should not be rewritten.

Fixes <rdar://problem/16492408>

llvm-svn: 205565
2014-04-03 20:51:08 +00:00
Rui Ueyama 69fcde8b0a Expand 'auto' that's hard for human to deduce its real type.
llvm-svn: 205564
2014-04-03 20:47:50 +00:00
NAKAMURA Takumi 4dca4d8bbd unconditional-branch.ll is broken for targeting x86_64-cygming. Add an explicit triple for now.
llvm-svn: 205563
2014-04-03 20:40:37 +00:00
Tom Stellard a0150cb6a9 R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4

Fixes Arithm/Absdiff.Mat/3 OpenCV test

Patch by: Bruno Jiménez

llvm-svn: 205562
2014-04-03 20:19:29 +00:00
Tom Stellard 7ed0b5235a R600/SI: Lower 64-bit immediates using REG_SEQUENCE
llvm-svn: 205561
2014-04-03 20:19:27 +00:00
NAKAMURA Takumi c5acee0f20 Revert r205551, "Attempt to XFAIL this on mingw and cygwin hosts." It didn't fail on cygming.
That said, it emits errors to the stderr (with exit(0));

  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_SECREL
  error: failed to compute relocation: IMAGE_REL_I386_DIR32

llvm-svn: 205560
2014-04-03 20:08:02 +00:00
NAKAMURA Takumi 8ff866c24e llvm/test/CodeGen/X86/peephole-multiple-folds.ll: Relax expressions to satisfy win32.
llvm-svn: 205559
2014-04-03 20:07:51 +00:00
Rui Ueyama 4469ce6c7b Add empty() to atom_collection.
"x.empty()" is more idiomatic than "x.size() == 0". This patch is to
add such method and use it in LLD.

Differential Revision: http://llvm-reviews.chandlerc.com/D3279

llvm-svn: 205558
2014-04-03 19:51:14 +00:00
Fariborz Jahanian 275542a40e vector [Sema]. Check for proper use of 's' char prefix
(which indicates vector expression is a string of hex
values) instead of crashing in code gen. // rdar://16492792

llvm-svn: 205557
2014-04-03 19:43:01 +00:00
Tobias Grosser 72cebdec2e Add another hint for fixing check-polly errors to get_started.html
Reversed the order in which LD_LIBRARY_PATH is defined in order to make sure the
${CLOOG_INSTALL} prefix is found first.

Contributed-by: Christian Bielert <cib123@googlemail.com>
llvm-svn: 205556
2014-04-03 19:38:38 +00:00
Ed Maste 0fdeb7158e Avoid crash if symbol returns a null name
llvm-svn: 205555
2014-04-03 19:27:39 +00:00
Reid Kleckner d3923aaa6e -fms-extensions: Error out on #pragma init_seg
By ignoring this pragma with a warning, we're essentially miscompiling
the user's program.  WebKit / Blink use this pragma to disable dynamic
initialization and finalization of some static data, and running the
dtors crashes the program.

Error out for now, so that /fallback compiles the TU correctly with
MSVC.  This pragma should be implemented some time this month, and we
can remove this hack.

llvm-svn: 205554
2014-04-03 19:04:24 +00:00
Tobias Grosser d7c5e51627 Note of last Polly phone call
llvm-svn: 205553
2014-04-03 18:56:13 +00:00
Rui Ueyama e8fa7c079e Remove "virtual" and add "override".
Seems clang-modernize couldn't add "override" to nested classes, so
doing it by hand. Also removed unused virtual member function that
is not overriding anything, that seems to have been added by mistake.

llvm-svn: 205552
2014-04-03 18:25:36 +00:00
Eric Christopher 5bdaea85cb Attempt to XFAIL this on mingw and cygwin hosts. The line table on
these is very much off and is more than just the branch
from this bug incorrect:

Address            Line   Column File   ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x30830a0100000002      3      0      1   0             0  is_stmt
0x30830a0100000008      3      0      1   0             0  is_stmt end_sequence

llvm-svn: 205551
2014-04-03 18:23:52 +00:00
Rui Ueyama 2b2ac91fab Remove "this->".
For most member function calls we do not use "this->" in this file.
Remove the rest for consistency.

llvm-svn: 205550
2014-04-03 18:13:14 +00:00
Tobias Grosser ca61be3ac2 Add a paragraph describing how to configure the python interpreter.
Contributed-by: cib123@googlemail.com
llvm-svn: 205549
2014-04-03 18:12:13 +00:00
Roman Divacky 6150990d59 Revert r205436:
Extend the SSE2 comment lexing to AVX2. Only 16byte align when not on AVX2.

        This provides some 3% speedup when preprocessing gcc.c as a single file.


The patch is wrong, it always uses SSE2, and when I fix that there's no speedup
at all. I am not sure where the 3% came from previously.

--Thi lie, and those below, will be ignored--

M    Lex/Lexer.cpp

llvm-svn: 205548
2014-04-03 18:04:52 +00:00
Eli Bendersky 9966b26dac Fix PR19270 - type mismatch caused by invalid optimization.
Patch by Jingyue Wu.

llvm-svn: 205547
2014-04-03 17:51:58 +00:00
Eric Christopher bc79fddb9a Loosen up check so that we can pass on platforms that generate
slightly more verbose than needed line tables, e.g.:

Address            Line   Column File   ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x0000000000000000      1      0      1   0             0  is_stmt
0x0000000000000000      1      0      1   0             0  is_stmt prologue_end
0x0000000000000010      2      0      1   0             0  is_stmt
0x0000000000000018      4      0      1   0             0  is_stmt

these should probably be looked at, but it isn't affecting the correctness
of the testcase.

llvm-svn: 205546
2014-04-03 17:40:08 +00:00
Saleem Abdulrasool 717c991923 ARM: update even more tests
More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

llvm-svn: 205545
2014-04-03 17:35:22 +00:00
Jim Ingham 2f4693aa77 Get "dis -c -s" working again.
pr19324

llvm-svn: 205544
2014-04-03 17:16:17 +00:00
Faisal Vali b90b211eea Teach getTemplateInstantiationPattern to deal with generic lambdas.
No functionality change.

When determining the pattern for instantiating a generic lambda call operator specialization - we must not go drilling down for the 'prototype' (i.e. as written) pattern - rather we must use our partially transformed  pattern (whose DeclRefExprs are wired correctly to any enclosing lambda's decls that should be mapped correctly in a local instantiation scope) that is the templated pattern of the specialization's primary template (even though the primary template might be instantiated from a 'prototype' member-template).  Previously, the drilling down was haltted by marking the instantiated-from primary template as a member-specialization (incorrectly). 

This prompted Richard to remark (http://llvm-reviews.chandlerc.com/D1784?id=4687#inline-10272) 
"It's a bit nasty to (essentially) set this bit incorrectly. Can you put the check into getTemplateInstantiationPattern instead?"

In my reckless youth, I chose to ignore that comment.  With the passage of time, I have come to learn the value of bowing to the will of the angry Gods ;) 

llvm-svn: 205543
2014-04-03 16:32:21 +00:00
Dmitri Gribenko 265f2f0440 ArrayRef: use std::vector::data() now that we are building in C++11 mode
llvm-svn: 205542
2014-04-03 16:29:11 +00:00
Saleem Abdulrasool 7258735fa0 ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default.  This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

llvm-svn: 205541
2014-04-03 16:01:44 +00:00
Tim Northover 01b4aa9437 ARM: tell LLVM about zext properties of ldrexb/ldrexh
Implementing this via ComputeMaskedBits has two advantages:
  + It actually works. DAGISel doesn't deal with the chains properly
    in the previous pattern-based solution, so they never trigger.
  + The information can be used in other DAG combines, as well as the
    trivial "get rid of truncs". For example if the trunc is in a
    different basic block.

rdar://problem/16227836

llvm-svn: 205540
2014-04-03 15:10:35 +00:00
Ed Maste 0dcccf7bf3 Add explict dependencies on swig .i files for cmake builds
llvm.org/pr19316

llvm-svn: 205539
2014-04-03 15:03:11 +00:00
Daniel Sanders a934837e48 [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's
Summary:
test/MC/Mips/<isa1>/invalid-<isa2>.s
    Test that <isa1> does not support <isa2>'s instructions.
test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s
    Things that should be invalid but currently aren't. Will XPASS if any
    become invalid.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3262

llvm-svn: 205538
2014-04-03 14:14:22 +00:00
Daniel Sanders 442f1a12f1 [mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3246

llvm-svn: 205537
2014-04-03 13:21:51 +00:00
Logan Chien 749763eaf7 Code cleanup (re-indent)
llvm-svn: 205536
2014-04-03 13:12:44 +00:00
Tim Northover 70450c59a4 ARM: skip cmpxchg failure barrier if ordering is monotonic.
The terminal barrier of a cmpxchg expansion will be either Acquire or
SequentiallyConsistent. In either case it can be skipped if the
operation has Monotonic requirements on failure.

rdar://problem/15996804

llvm-svn: 205535
2014-04-03 13:06:54 +00:00
Alexey Samsonov 425314a65f [TSan] Fix a rare deadlock on multithreaded fork.
If a multi-threaded program calls fork(), TSan ignores all memory accesses
in the child to prevent deadlocks in TSan runtime. This is OK, as child is
probably going to call exec() as soon as possible. However, a rare deadlocks
could be caused by ThreadIgnoreBegin() function itself.

ThreadIgnoreBegin() remembers the current stack trace and puts it into the
StackDepot to report a warning later if a thread exited with ignores enabled.
Using StackDepotPut in a child process is dangerous: it locks a mutex on
a slow path, which could be already locked in a parent process.

The fix is simple: just don't put current stack traces to StackDepot in
ThreadIgnoreBegin() and ThreadIgnoreSyncBegin() functions if we're
running after a multithreaded fork. We will not report any
"thread exited with ignores enabled" errors in this case anyway.

Submitting this without a testcase, as I believe the standalone reproducer
is pretty hard to construct.

llvm-svn: 205534
2014-04-03 12:51:26 +00:00
Samuel Benzaquen 5548eadb1c Revert "Add support for named values in the parser."
This was submitted before it was ready.

This reverts commit 62060a01e095cf35eb9ca42a333752d12714f35c.

llvm-svn: 205533
2014-04-03 12:50:47 +00:00
Zoran Jovanovic cabf0f41e0 Implementation of 16-bit microMIPS instructions MFHI and MFLO.
Differential Revision: http://llvm-reviews.chandlerc.com/D3141

llvm-svn: 205532
2014-04-03 12:47:34 +00:00
Alexey Samsonov b4525218d4 [TSan] Fix a typo ThreadIgnoreSyncEnd. Found by inspection
llvm-svn: 205531
2014-04-03 12:28:16 +00:00
Daniel Sanders f7b32291ad [mips] Add initial (experimental) MIPS-IV support.
Summary:
Adds the 'mips4' processor and a simple test of the ELF e_flags.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I made one small change to the testcase so that it uses
mips64-unknown-linux instead of mips4-unknown-linux.

This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok
because it's supposed to be there anyway and it turns out that
FeatureCondMov is not a predicate of any instructions at the moment
(this is a bug that hasn't been noticed because there are no targets
without the conditional move instructions yet).

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3244

llvm-svn: 205530
2014-04-03 12:13:36 +00:00
Eric Christopher bfb38badc1 Fix for PR 19261:
llc doesn't generate nodes for unconditional fall-through branches for targets
without FastISel implementation (X86 has it, but can be disabled by
"-fast-isel=false") in SelectionDAGBuilder::visitBr().

So for line 4 in the following testcase

1: void foo(int i){
2:   switch(i){
3:   default:
4:     break;
5:   }
6:   return;
7: }

there is no corresponding line in .debug_line section, and a debugger
cannot set a breakpoint at line 4.

Fix this by always emitting a branch when we're not optimizing and add a
testcase to ensure that there's code on every line we'd want to break.

Patch by Daniil Fukalov.

llvm-svn: 205529
2014-04-03 12:11:51 +00:00
Zoran Jovanovic 842f20ef0b MicroMIPS specific little endian fixup data byte ordering.
Differential Revision: http://llvm-reviews.chandlerc.com/D3245

llvm-svn: 205528
2014-04-03 12:01:01 +00:00
Daniel Jasper 5c33265c9e clang-format: Prefer an additional line-break over hanging indent.
Don't allow the RHS of an operator to be split over multiple
lines unless there is a line-break right after the operator.

Before:
  if (aaaa && bbbbb || // break
                  cccc) {
  }

After:
  if (aaaa &&
      bbbbb || // break
          cccc) {
  }

In most cases, this seems to increase readability.

llvm-svn: 205527
2014-04-03 12:00:33 +00:00
Daniel Jasper 2b7556ec16 x
llvm-svn: 205526
2014-04-03 12:00:27 +00:00
Tim Northover c882eb0723 ARM: expand atomic ldrex/strex loops in IR
The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded
at MachineInstr emission time had grown to be extremely large and
involved, to account for the subtly different code needed for the
various flavours (8/16/32/64 bit, cmpxchg/add/minmax).

Moving this transformation into the IR clears up the code
substantially, and makes future optimisations much easier:

1. an atomicrmw followed by using the *new* value can be more
   efficient. As an IR pass, simple CSE could handle this
   efficiently.
2. Making use of cmpxchg success/failure orderings only has to be done
   in one (simpler) place.
3. The common "cmpxchg; did we store?" idiom can be exposed to
   optimisation.

I intend to gradually improve this situation within the ARM backend
and make sure there are no hidden issues before moving the code out
into CodeGen to be shared with (at least ARM64/AArch64, though I think
PPC & Mips could benefit too).

llvm-svn: 205525
2014-04-03 11:44:58 +00:00
Stepan Dyatkovskiy 6207a4dadc PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.

llvm-svn: 205524
2014-04-03 11:29:15 +00:00
Silviu Baranga a3106e6847 [ARM] When generating a vpaddl node the input lane type is not always the type of the
add operation since extract_vector_elt can perform an extend operation. Get the input lane
type from the vector on which we're performing the vpaddl operation on and extend or
truncate it to the output type of the original add node.

llvm-svn: 205523
2014-04-03 10:44:27 +00:00