Commit Graph

117030 Commits

Author SHA1 Message Date
Hans Wennborg ae0254dabc Switch lowering: cluster adjacent fall-through cases even at -O0
It's cheap to do, and codegen is much faster if cases can be merged
into clusters.

llvm-svn: 236905
2015-05-08 21:23:39 +00:00
Daniel Berlin c67979bf4d Add a comment about DepthFirstIterator's skipchildren behavior
llvm-svn: 236904
2015-05-08 21:17:24 +00:00
Renato Golin f5f373fcf1 TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.

Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).

The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.

The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.

The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
 * A bogus neon-vfpv3 alias (neon defaults to vfp3)
 * armv5/v6
 * {fp4/fp5}-{sp/dp}-d16

Next steps:
 * Port Clang's ARCH/EXT parsing to use this library.
 * Create a TableGen back-end to generate this information.
 * Run this TableGen process regardless of which back-ends are built.
 * Expose more information and rename it to TargetDescription.
 * Continue re-factoring Clang to use as much of it as possible.

llvm-svn: 236900
2015-05-08 21:04:27 +00:00
Diego Novillo 0aaff4795b Update Function::getContext documentation. NFC.
llvm-svn: 236899
2015-05-08 21:01:29 +00:00
Pete Cooper e4bb07ecff [Fast-ISel] Clear kill flags on registers replaced by updateValueMap.
When selecting an extract instruction, we don't actually generate code but instead work out which register we are reading, and rewrite uses of the extract def to the source register.  This is done via updateValueMap,.

However, its possible that the source register we are rewriting *to* to also have uses.  If those uses are after a kill of the value we are rewriting *from* then we have uses after a kill and the verifier fails.

This code checks for the case where the to register is also used, and if so it clears all kill on the from register.  This is conservative, but better that always clearing kills on the from register.

llvm-svn: 236897
2015-05-08 20:46:54 +00:00
Brendon Cahoon bece8edcdd [Hexagon] Generate more hardware loops
Refactored parts of the hardware loop pass to generate
more. Also, added more tests.

Differential Revision: http://reviews.llvm.org/D9568

llvm-svn: 236896
2015-05-08 20:18:21 +00:00
Sanjoy Das 14f5080aa1 [BasicAA] Fix zext & sext handling
Summary:

There are several unhandled edge cases in BasicAA's GetLinearExpression
method. This changes fixes outstanding issues, including zext / sext of
a constant with the sign bit set, and the refusal to decompose zexts or
sexts of wrapping arithmetic.

Test Plan: Unit tests added in //q.ext.ll//.

Patch by Nick White.

Reviewers: hfinkel, sanjoy

Reviewed By: hfinkel, sanjoy

Subscribers: sanjoy, llvm-commits, hfinkel

Differential Revision: http://reviews.llvm.org/D6682

llvm-svn: 236894
2015-05-08 18:58:55 +00:00
David Blaikie b340f0a7bc Replace branch-to-unreachable with assertion.
llvm-svn: 236893
2015-05-08 18:52:28 +00:00
Pat Gavlin 7afaed2847 Fix a docs build break introduced by rL236888.
llvm-svn: 236891
2015-05-08 18:37:49 +00:00
Pete Cooper 7f7c9f1dad [X86] Fast-ISel was incorrectly always killing the source of a truncate.
A trunc from i32 to i1 on x86_64 generates an instruction such as

%vreg19<def> = COPY %vreg9:sub_8bit<kill>; GR8:%vreg19 GR32:%vreg9

However, the copy here should only have the kill flag on the 32-bit path, not the 64-bit one.
Otherwise, we are killing the source of the truncate which could be used later in the program.

llvm-svn: 236890
2015-05-08 18:29:42 +00:00
Pat Gavlin cc0431d1c0 Extend the statepoint intrinsic to allow statepoints to be marked as transitions from GC-aware code to code that is not GC-aware.
This changes the shape of the statepoint intrinsic from:

  @llvm.experimental.gc.statepoint(anyptr target, i32 # call args, i32 unused, ...call args, i32 # deopt args, ...deopt args, ...gc args)

to:

  @llvm.experimental.gc.statepoint(anyptr target, i32 # call args, i32 flags, ...call args, i32 # transition args, ...transition args, i32 # deopt args, ...deopt args, ...gc args)

This extension offers the backend the opportunity to insert (somewhat) arbitrary code to manage the transition from GC-aware code to code that is not GC-aware and back.

In order to support the injection of transition code, this extension wraps the STATEPOINT ISD node generated by the usual lowering lowering with two additional nodes: GC_TRANSITION_START and GC_TRANSITION_END. The transition arguments that were passed passed to the intrinsic (if any) are lowered and provided as operands to these nodes and may be used by the backend during code generation.

Eventually, the lowering of the GC_TRANSITION_{START,END} nodes should be informed by the GC strategy in use for the function containing the intrinsic call; for now, these nodes are instead replaced with no-ops.

Differential Revision: http://reviews.llvm.org/D9501

llvm-svn: 236888
2015-05-08 18:07:42 +00:00
Jingyue Wu 78b0d51cd0 [NoTTI] reject negative scale in addressing mode
Summary:
I noticed this bug when deubging a WIP on LSR. I wonder whether and how we
should add a regression test for this.

Test Plan: no tests failed.

Reviewers: atrick

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D9536

llvm-svn: 236887
2015-05-08 18:07:24 +00:00
Pete Cooper 85b1c48b20 Clear kill flags on all used registers when sinking instructions.
The test here was sinking the AND here to a lower BB:

	%vreg7<def> = ANDWri %vreg8, 0; GPR32common:%vreg7,%vreg8
	TBNZW %vreg8<kill>, 0, <BB#1>; GPR32common:%vreg8

which meant that vreg8 was read after it was killed.

This commit changes the code from clearing kill flags on the AND to clearing flags on all registers used by the AND.

llvm-svn: 236886
2015-05-08 17:54:32 +00:00
Pete Cooper ff5064a188 80 cols fix since i'm looking at this function anyway. NFC
llvm-svn: 236885
2015-05-08 17:54:29 +00:00
Pete Cooper eaef4bcd40 Remove duplicate cmake target I added in r236792.
Thanks to Daniel Jasper for pointing out the mistake.

llvm-svn: 236881
2015-05-08 16:59:53 +00:00
Douglas Katzman 049887b252 Unbreak build: Makefile must have the same change as CMakeLists.txt
This was omitted from http://reviews.llvm.org/D9441
(the irony is that that was to detect omissions in something else)

llvm-svn: 236878
2015-05-08 16:39:59 +00:00
Brendon Cahoon df43e68629 [Hexagon] Update AnalyzeBranch, etc target hooks
Improved the AnalyzeBranch, InsertBranch, and RemoveBranch
functions in order to handle more of our branch instructions.
This requires changes to analyzeCompare and PredicateInstructions.
Specifically, we've added support for new value compare jumps,
improved handling of endloop, added more compare instructions,
and improved support for predicate instructions.

Differential Revision: http://reviews.llvm.org/D9559

llvm-svn: 236876
2015-05-08 16:16:29 +00:00
Douglas Katzman ec1fc97e5d Prevent further errors of omission when adding backend names.
Differential Revision: http://reviews.llvm.org/D9441

llvm-svn: 236865
2015-05-08 15:34:12 +00:00
Andrea Di Biagio 84e22b9096 [X86] Teach 'getTargetShuffleMask' how to look through ISD::WrapperRIP when decoding a PSHUFB mask.
The function 'getTargetShuffleMask' already knows how to deal with PSHUFB nodes
where the mask node is a load from constant pool, and the constant pool node
is wrapped by a X86ISD::Wrapper node. This patch extends that logic by teaching
it how to also look through X86ISD::WrapperRIP.

This helps function combineX86ShufflesRecusively to combine more shuffle
sequences containing PSHUFB nodes if we are in RIPRel PIC mode.

Before this change, llc (with -relocation-model=pic -march=x86-64) was unable
to decode a pshufb where the mask was loaded from a constant pool. For example,
the no-op shuffle from test 'x86-fold-pshufb.ll' was not folded into its
operand, so instead of generating a single 'movaps' the backend always
generated a sub-optimal 'movdqa + pshufb' sequence.

Added test x86-fold-pshufb.ll.

llvm-svn: 236863
2015-05-08 15:11:07 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
2015-05-08 14:25:11 +00:00
James Y Knight 38514d2177 Fix test added in r236850 for OSX builders.
Need to specify triple so that llvm emits the asm syntax that the
test expected.

llvm-svn: 236855
2015-05-08 14:04:54 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
2015-05-08 13:52:04 +00:00
James Y Knight 284e7b3d6c Fix alignment checks in MergeConsecutiveStores.
1) check whether the alignment of the memory is sufficient for the
*merged* store or load to be efficient.

Not doing so can result in some ridiculously poor code generation, if
merging creates a vector operation which must be aligned but isn't.

2) DON'T check that the alignment of each load/store is equal. If
you're merging 2 4-byte stores, the first *might* have 8-byte
alignment, but the second certainly will have 4-byte alignment. We do
want to allow those to be merged.

llvm-svn: 236850
2015-05-08 13:47:01 +00:00
Igor Laevsky 9d3932bf96 Fix coding standart based on post submit comments.
Differential Revision: http://reviews.llvm.org/D7760

llvm-svn: 236849
2015-05-08 13:17:22 +00:00
John Brawn 50ed9470dc [ARM] Reject invalid -march values
Restructure Triple::getARMCPUForArch so that invalid values will
return nullptr, while retaining the behaviour that an argument
specifying no particular architecture version will give a default
CPU. This will be used by clang to give an error on invalid -march
values.

Also restructure the extraction of the architecture version from
the MArch string a little to hopefully make what it's doing clearer.

Differential Revision: http://reviews.llvm.org/D9599

llvm-svn: 236845
2015-05-08 12:52:02 +00:00
Denis Protivensky 159a49e5d6 Fix gcc warning of different enum and non-enum types in ternary
Make '0' literal explicitly unsigned with '0u'.
This appeared after r236775.

llvm-svn: 236838
2015-05-08 12:21:03 +00:00
Toma Tabacu 8b3345ba7c [mips] Only use FGR_{32,64} in TableGen descriptions. NFC.
Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9566

llvm-svn: 236835
2015-05-08 12:15:04 +00:00
Igor Laevsky 5e23e16c6c This change is refactoring only. It moves basic block normalization for invokes to happen before replacement of a call with safepoint in "ReplaceWithStatepoint". Previously it was partly done before replacement of calls with safepoint and partly after call replacement but before RAUW's for gc_relocates, which was confusing.
llvm-svn: 236829
2015-05-08 11:59:09 +00:00
Vasileios Kalintiris 42544d6472 [mips] Emit the .insn directive for empty basic blocks.
Summary:
In microMIPS, labels need to know whether they are on code or data. This is
indicated with STO_MIPS_MICROMIPS and can be inferred by being followed
by instructions. For empty basic blocks, we can ensure this by emitting the
.insn directive after the label.

Also, this fixes some failures in our out-of-tree microMIPS buildbots, for the
exception handling regression tests under: SingleSource/Regression/C++/EH

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9530

llvm-svn: 236815
2015-05-08 09:10:15 +00:00
Simon Atanasyan 8eb9d1bf12 [yaml2elf] Replace error message by assert call in writeSectionContent methods
Now caller of ELFState::writeSectionContent() methods is responsible to check
a section type and selects an appropriate writeSectionContent method.
So unexpected section type inside writeSectionContent method indicates
a wrong usage of the method and should be guarded by assert.

llvm-svn: 236808
2015-05-08 07:05:04 +00:00
Simon Atanasyan 40e7eb166a [llvm-readobj/obj2yaml/yaml2obj] Support MIPS machine ELF header flags
llvm-svn: 236807
2015-05-08 07:04:59 +00:00
Eric Christopher 81fa35ca24 Now that we have a soft-float attribute, use it instead of the
hard coded command line option for the Mips soft float tests.

llvm-svn: 236801
2015-05-08 00:57:22 +00:00
David Blaikie 60310f2720 [opaque pointer type] Explicit pointee type for GEPOperator/GEPConstantExpr.
Also a couple of other changes to avoid use of
PointerType::getElementType here & there too.

llvm-svn: 236799
2015-05-08 00:42:26 +00:00
Alexey Samsonov 21a3381a38 Update CMake flags, LibFuzzer comments and docs for new -fsanitize-coverage= flags.
llvm-svn: 236797
2015-05-07 23:33:24 +00:00
Eric Christopher 54966ebc54 InMips16HardFloat was only being set conditional on whether or
not IsSoftFloat was set so remove it from here simplifying the
accessor.

llvm-svn: 236795
2015-05-07 23:10:23 +00:00
Eric Christopher e8ae3e3acd Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to match
some incoming changes and the general scheme used by features (use/has).

llvm-svn: 236794
2015-05-07 23:10:21 +00:00
Pete Cooper fb13c57669 Add yaml-bench to the list of tools make check needs to run
llvm-svn: 236792
2015-05-07 22:53:11 +00:00
Alexey Samsonov ebd22570b2 Delete unused createSanitizerCoverageModulePass overload.
llvm-svn: 236791
2015-05-07 22:46:06 +00:00
NAKAMURA Takumi 723b449df5 [CMake] llvm/test/YAMLParser requires yaml-bench. This fixes r236754.
llvm-svn: 236787
2015-05-07 22:24:58 +00:00
Ismail Pazarbasi 416071e20a Revert "SanitizerCoverage: Use `createSanitizerCtor` to create ctor and call init"
Will fix tomorrow. Unbreak build bots now.

llvm-svn: 236786
2015-05-07 22:17:48 +00:00
Matthias Braun f45afee3dc Fix typo.
llvm-svn: 236785
2015-05-07 22:16:10 +00:00
Pete Cooper ba593ad3f3 Clear kill flags in tail duplication.
If we duplicate an instruction then we must also clear kill flags on any uses we rewrite.
Otherwise we might be killing a register which was used in other BBs.

For example, here the entry BB ended up with these instructions, the ADD having been tail duplicated.

	%vreg24<def> = t2ADDri %vreg10<kill>, 1, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg24 rGPR:%vreg10
	%vreg22<def> = COPY %vreg10; GPR:%vreg22 rGPR:%vreg10

	The copy here is inserted after the add and so needs vreg10 to be live.

llvm-svn: 236782
2015-05-07 21:48:26 +00:00
Ismail Pazarbasi d6291964fb When checking msan.module_ctor, use CHECK-LABEL instead of CHECK
llvm-svn: 236781
2015-05-07 21:47:25 +00:00
Ismail Pazarbasi 5bc0feb3de SanitizerCoverage: Use `createSanitizerCtor` to create ctor and call init
Reviewers: kcc, samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8780

llvm-svn: 236780
2015-05-07 21:43:28 +00:00
Ismail Pazarbasi e5048e153a MSan: Use `createSanitizerCtor` to create ctor, and call `__msan_init`
Reviewers: kcc, eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8781

llvm-svn: 236779
2015-05-07 21:41:52 +00:00
Ismail Pazarbasi 2d4ae9f0d5 TSan: Use `createSanitizerCtor` to create ctor, and call `__tsan_init`
Reviewers: kcc, dvyukov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8779

llvm-svn: 236778
2015-05-07 21:41:23 +00:00
Ismail Pazarbasi 09c3709e75 ASan: Use `createSanitizerCtor` to create ctor, and call `__asan_init`
Reviewers: kcc, samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8778

llvm-svn: 236777
2015-05-07 21:40:46 +00:00
Matthias Braun d04893fa36 Change getTargetNodeName() to produce compiler warnings for missing cases, fix them
llvm-svn: 236775
2015-05-07 21:33:59 +00:00
Kostya Serebryany beb24c38e7 [lib/Fuzzer] change the way we use taint information for fuzzing. Now, we run a single unit and collect suggested mutations based on tracing+taint data, then apply the suggested mutations one by one. The previous scheme was slower and more complex.
llvm-svn: 236772
2015-05-07 21:02:11 +00:00
Steven Wu aed94a0bba Use auto instead of the long type name. NFC.
llvm-svn: 236768
2015-05-07 19:56:23 +00:00
Pete Cooper f52123b454 [AArch64] Fix sext/zext folding in address arithmetic.
We were accidentally folding a sign/zero extend in to address arithmetic in a different BB when the extend wasn't available there.

Cross BB fast-isel isn't safe, so restrict this to only when the extend is in the same BB as the use.

llvm-svn: 236764
2015-05-07 19:21:36 +00:00
Alex Lorenz 712cedaac5 Fix r236754: Add the missing yaml-bench dir to the makefile for utils.
This commit adds the missing yaml-bench utility to the
makefile in utils. It was missing before and it caused
the regression tests to fail on some buildbots when llvm-lit 
couldn't find yaml-bench when llvm was built without 
cmake after I committed r236754.

llvm-svn: 236761
2015-05-07 18:48:48 +00:00
Sergey Dmitrouk 9a6caea967 Disable r235989 "Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes""
Will be re-enabled with missing changes for ConstantFPSDNode and
fixes for wrong locations due to constant coalescing.

llvm-svn: 236758
2015-05-07 18:33:50 +00:00
Kostya Serebryany 7d470cfb0c [lib/Fuzzer] minor refactoring/simplification, NFC
llvm-svn: 236757
2015-05-07 18:32:29 +00:00
Nemanja Ivanovic f3c94b1e3c Add VSX Scalar loads and stores to the PPC back end
This patch corresponds to review:
http://reviews.llvm.org/D9440

It adds a new register class to the PPC back end to contain single precision
values in VSX registers. Additionally, it adds scalar loads and stores for
VSX registers.

llvm-svn: 236755
2015-05-07 18:24:05 +00:00
Alex Lorenz e4bcfbf5dc YAML: Enable the YAMLParser tests.
This commit enables the tests located in test/YAMLParser directory.
Those tests were never actually enabled, as llvm-lit didn't pick up the
files with the 'data' extension. The commit renames those test files to files
with the 'test' extension so that llvm-lit would find them.

This commit also modifies yaml-bench so that it returns an error status
if an error occurred during parsing. It also adds the '-use-color'
command line option to yaml-bench (to make sure that file check matches
the error messages in the output stream).

This commit modifies some of the renamed tests so that they wouldn't
fail. It gets rid of XFAILs and uses the 'not' command instead for
some of the tests that have to fail during parsing. This commit
also adds some 'FIXME' comments to a couple of tests that are
supposed to fail but currently pass because of various bugs
in the implementation of the yaml parser.

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9448

llvm-svn: 236754
2015-05-07 18:08:46 +00:00
David Blaikie d9d900c05b Recommit r236670: [opaque pointer type] Pass explicit pointer type through GEP constant folding""
Clang regressions were caused by more stringent assertion checking
introduced by this change. Small fix needed to clang has been committed
in r236751.

llvm-svn: 236752
2015-05-07 17:28:58 +00:00
Diego Novillo de5b8016ab Fix information loss in branch probability computation.
Summary:
This addresses PR 22718. When branch weights are too large, they were
being clamped to the range [1, MaxWeightForBB]. But this clamping is
only applied to edges that go outside the range, so it distorts the
relative branch probabilities.

This patch changes the weight calculation to scale every branch so the
relative probabilities are preserved. The scaling is done differently
now. First, all the branch weights are added up, and if the sum exceeds
32 bits, it computes an integer scale to bring all the weights within
the range.

The patch fixes an existing test that had slightly wrong branch
probabilities due to the previous clamping. It now gets branch weights
scaled accordingly.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9442

llvm-svn: 236750
2015-05-07 17:22:06 +00:00
Jozef Kolek cf98462818 [mips][microMIPSr6] Implement JIALC and JIC instructions
This patch implements JIALC and JIC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8389

llvm-svn: 236748
2015-05-07 17:12:23 +00:00
Michael Zolotukhin de63aace8a Populate list of vectorizable functions for Accelerate library.
Summary:
This patch adds majority of supported by Accelerate library functions to the
list of vectorizable functions.

The full list of available vector functions could be found here:
https://developer.apple.com/library/mac/documentation/Performance/Conceptual/vecLib/index.html

Test Plan: Unit tests are added.

Reviewers: hfinkel, aschwaighofer, nadav

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9543

llvm-svn: 236747
2015-05-07 17:11:51 +00:00
Matt Arsenault 585b566278 R600: Fix comment that mentions AMDIL
llvm-svn: 236745
2015-05-07 17:02:32 +00:00
Sanjay Patel 5b373cacf2 Use intrinsic pattern to make a simpler match
This is a follow-on to r236740 where I took Andrea's advice
in D9504 to remove a redundant pattern...except that I removed
the wrong pattern!

AFAICT, there is no change in the final code produced because 
subsequent passes would clean up the extra instructions created
by the more complicated pattern.

llvm-svn: 236743
2015-05-07 16:51:12 +00:00
Steven Wu 94746694ca Fix another hang caused by ManagedStatic in SignalHandler
Fix two other variables that might cause the same hang fixed in r235914.
The hang is caused by constructing ManagedStatic in signalhandler. In
this case, if FileToRemove or CallBacksToRun is not contructed, it means
there is no work to do.

llvm-svn: 236741
2015-05-07 16:20:51 +00:00
Sanjay Patel a9f6d3505d [x86] eliminate unnecessary shuffling/moves with unary scalar math ops (PR21507)
Finish the job that was abandoned in D6958 following the refactoring in
http://reviews.llvm.org/rL230221:

1. Uncomment the intrinsic def for the AVX r_Int instruction.
2. Add missing r_Int entries to the load folding tables; there are already
   tests that check these in "test/Codegen/X86/fold-load-unops.ll", so I
   haven't added any more in this patch.
3. Add patterns to solve PR21507 ( https://llvm.org/bugs/show_bug.cgi?id=21507 ).

So instead of this:

  movaps	%xmm0, %xmm1
  rcpss	%xmm1, %xmm1
  movss	%xmm1, %xmm0

We should now get:

  rcpss	%xmm0, %xmm0

And instead of this:

  vsqrtss	%xmm0, %xmm0, %xmm1
  vblendps	$1, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm1[0],xmm0[1,2,3]

We should now get:

  vsqrtss	%xmm0, %xmm0, %xmm0


Differential Revision: http://reviews.llvm.org/D9504

llvm-svn: 236740
2015-05-07 15:48:53 +00:00
Hans Wennborg 44faaa7aa4 Switch lowering: handle zero-weight branch probabilities
After r236617, branch probabilities are no longer guaranteed to be >= 1. This
patch makes the swich lowering code handle that correctly, without bumping the
branch weights by 1 which might cause overflow and skews the probabilities.

Covered by @zero_weight_tree in test/CodeGen/X86/switch.ll.

llvm-svn: 236739
2015-05-07 15:47:15 +00:00
Simon Atanasyan 04d9e653ed [obj2yaml/yaml2obj] Add SHT_MIPS_ABIFLAGS section support
This change adds support for the SHT_MIPS_ABIFLAGS section
reading/writing to the obj2yaml and yaml2obj tools.

llvm-svn: 236738
2015-05-07 15:40:48 +00:00
Simon Atanasyan c914de2770 [llvm-readobj] Print .MIPS.abiflags section content
This change adds new flag -mips-abi-flags to the llvm-readobj. This flag
forces printing of .MIPS.abiflags section content.

https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.2.1._.MIPS.abiflags

llvm-svn: 236737
2015-05-07 15:40:35 +00:00
Simon Atanasyan fee03b1be8 [MIPS] Move MIPS ABI flags structure constants to the separate header
http://reviews.llvm.org/D9517

The separate header file allows to reuse the MIPS ABI flags structure
constants in other LLVM tools like the llvm-readobj.

No functional changes.

llvm-svn: 236732
2015-05-07 14:57:04 +00:00
Simon Atanasyan 67bdc799a7 [llvm-readobj/obj2yaml/yaml2obj] Support more MIPS ELF header flags
llvm-svn: 236728
2015-05-07 14:04:44 +00:00
Elena Demikhovsky 82cdd65123 Masked Gather and Scatter intrinsics - updated documentation.
llvm-svn: 236721
2015-05-07 12:25:11 +00:00
Elena Demikhovsky 29792e9a80 AVX-512: Added all forms of FP compare instructions for KNL and SKX.
Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 236714
2015-05-07 11:24:42 +00:00
Toma Tabacu 506cfd0b2b [mips] Add the SoftFloat MipsSubtarget feature.
Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled.

Reviewers: dsanders, echristo

Reviewed By: dsanders

Subscribers: jfb, llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9053

llvm-svn: 236713
2015-05-07 10:29:52 +00:00
NAKAMURA Takumi 2ce89617c9 Attributes.h: Fix incorrect \brief introduced in r236666. [-Wdocumentation]
llvm-svn: 236712
2015-05-07 10:18:56 +00:00
NAKAMURA Takumi 2a5bd54f4e Scalar/PlaceSafepoints.cpp: Fix a warning introduced in r228090. [-Wunused-variable]
llvm-svn: 236711
2015-05-07 10:18:46 +00:00
NAKAMURA Takumi 386c22c0ff llvm/test/CodeGen/X86/llc-override-mcpu-mattr.ll: Tweak not to be affected by x64 Calling Convention.
llvm-svn: 236710
2015-05-07 10:18:28 +00:00
Mehdi Amini 2668a487a7 Update InstCombine to transform aggregate loads into scalar loads.
Summary:
One step further getting aggregate loads and store being optimized
properly. This will only handle struct with one element at this point.

Test Plan: Added unit tests for the new supported cases.

Reviewers: chandlerc, joker-eph, joker.eph, majnemer

Reviewed By: majnemer

Subscribers: pete, llvm-commits

Differential Revision: http://reviews.llvm.org/D8339

Patch by Amaury Sechet.

From: Amaury Sechet <amaury@fb.com>
llvm-svn: 236695
2015-05-07 05:52:40 +00:00
Alexey Samsonov 3514f27456 [SanitizerCoverage] Introduce SanitizerCoverageOptions struct.
Summary:
This gives frontend more precise control over collected coverage
information. User can still override these options by passing
-mllvm flags.

No functionality change.

Test Plan: regression test suite.

Reviewers: kcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9539

llvm-svn: 236687
2015-05-07 01:00:31 +00:00
Justin Bogner 7b48749498 IR: Initialize DerefOrNullBytes in the AttrBuilder constructors
MSAN pointed out that this value is used uninitialized:

    http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/3678

llvm-svn: 236686
2015-05-07 00:56:34 +00:00
Justin Bogner 5a5c381ba9 InstrProf: Simplify looking up sections for coverage data
llvm-svn: 236685
2015-05-07 00:31:58 +00:00
Philip Reames 7a738dd94c [JumpThreading] Simplify comparisons when simplifying branches
If we have recognized that a conditional is constant at a particular location in the code (while trying to decide if we can simplify a conditional branch), we can eagerly replace that condition with a constant if it's definition is post dominated by the branch in question.

In practice, this ends up being a compile time savings at most. JumpThreading would have visited each using branch anyways. CVP would have visited the cmp itself again. Unless LVI gives up early, we shouldn't gain any addition power by doing this transformation early. What we do gain is simplicity and compile time.

Differential Revision: http://reviews.llvm.org/D9312

llvm-svn: 236684
2015-05-07 00:19:14 +00:00
Kostya Serebryany a407ddef27 [lib/Fuzzer] add dfsan_weak_hook_memcmp, enable the test that uses it, simplify the test runner
llvm-svn: 236683
2015-05-07 00:11:33 +00:00
Vince Harron d528112b41 Added support for building against Android API-9 SDK
Created an abstraction for log2, llvm::Log2 in Support/MathExtras.h

Hid Android problems inside of it

Differential Revision: http://reviews.llvm.org/D9467

llvm-svn: 236680
2015-05-07 00:05:26 +00:00
David Blaikie 567d0e5a90 Revert "[opaque pointer type] Pass explicit pointer type through GEP constant folding"
Causes regressions in Clang. Reverting while I investigate.

This reverts commit r236670.

llvm-svn: 236678
2015-05-06 23:56:21 +00:00
Akira Hatanaka 3058d0f080 Let llc and opt override "-target-cpu" and "-target-features" via command line
options.

This commit fixes a bug in llc and opt where "-mcpu" and "-mattr" wouldn't
override function attributes "-target-cpu" and "-target-features" in the IR.

Differential Revision: http://reviews.llvm.org/D9537

llvm-svn: 236677
2015-05-06 23:54:14 +00:00
Sanjoy Das 2e0d29fb09 [X86MCInst] Move LowerSTATEPOINT to inside X86AsmPrinter. NFC.
llvm-svn: 236676
2015-05-06 23:53:26 +00:00
Sanjoy Das 80876d5db3 [X86MCInst] Clean up LowerSTATEPOINT: variable names. NFC.
llvm-svn: 236675
2015-05-06 23:53:24 +00:00
Sanjoy Das abf15608a7 [Statepoints] Clean up PlaceSafepoints.cpp: de-duplicate code.
Common duplicated code and remove unnecessary code.

llvm-svn: 236674
2015-05-06 23:53:21 +00:00
Sanjoy Das 93abd813ec [Statepoints] Clean up PlaceSafepoints.cpp: variable naming.
Use CamelCase.  NFC.

llvm-svn: 236673
2015-05-06 23:53:19 +00:00
Sanjoy Das abe1c685ac [IRBuilder] Add a CreateGCStatepointInvoke.
Renames the original CreateGCStatepoint to CreateGCStatepointCall, and
moves invoke creating functionality from PlaceSafepoints.cpp to
IRBuilder.cpp.

This changes the labels generated for PlaceSafepoints/invokes.ll so use
a regex there to make the basic block labels more resilient.

llvm-svn: 236672
2015-05-06 23:53:09 +00:00
Akira Hatanaka 32b3760cf3 Factor out a function which determines the cpu and feature strings based on
command line options -mcpu and -mattr. NFC.

llvm-svn: 236671
2015-05-06 23:49:24 +00:00
David Blaikie e66a45fdb4 [opaque pointer type] Pass explicit pointer type through GEP constant folding
llvm-svn: 236670
2015-05-06 23:49:14 +00:00
Alex Lorenz 74b63ebd53 YAML: Fix crash in the skip method of KeyValueNode class.
This commit changes the 'skip' method in the 'KeyValueNode' class
to ensure that it doesn't dereference a null pointer when calling 
the 'skip' method of its value child node. It also adds a unittest
that ensures that the crash doesn't occur.

This change is motivated by a patch that implements parsing
of YAML block scalars (http://reviews.llvm.org/D9503), as one
of the unittests in that patch triggered this problem.

llvm-svn: 236669
2015-05-06 23:21:29 +00:00
Pete Cooper 2777d88745 Change typeIncompatible to return an AttrBuilder instead of new-ing an AttributeSet.
This makes use of the new API which can remove attributes from a set given a builder.

This is much faster than creating a temporary set and reduces llc time by about 0.3% which was all spent creating temporary attributes sets on the context.

llvm-svn: 236668
2015-05-06 23:19:56 +00:00
Pete Cooper a842c3fc57 Update all comments to match the previous commit. NFC
llvm-svn: 236667
2015-05-06 23:19:51 +00:00
Pete Cooper d2a44619e3 Add remove method to operate on AttrBuilder instead of AttributeSet.
Prior to this change we would have to construct a temporary AttributeSet (which isn't temporary at all given that its allocated on the context), just to contain the attributes in the builder, then call remove on that.

Now we can just remove any attributes from the (lightweight and really temporary) builder itself.

Will be used in a future commit to remove some temporary attributes sets.

llvm-svn: 236666
2015-05-06 23:19:43 +00:00
Justin Bogner 367a9f28c1 InstrProf: Give coverage its own errors instead of piggy backing on instrprof
Since the coverage mapping reader and the instrprof reader were
emitting a shared set of error codes, the error messages you'd get
back from llvm-cov were ambiguous about what was actually wrong. Add
another error category to fix this.

I've also improved the wording on a couple of the instrprof errors,
for consistency.

llvm-svn: 236665
2015-05-06 23:19:35 +00:00
Justin Bogner 0b13086366 InstrProf: Remove a function that just returns its argument (NFC)
llvm-svn: 236664
2015-05-06 23:15:55 +00:00
Alex Lorenz fe6f1865bc YAML: Extract the code that skips a comment into a separate method, NFC.
This commit extracts the code that skips over a YAML comment from 
the 'scanToNextToken' method into a separate 'skipComment' method.

This refactoring is motivated by a patch that implements parsing
of YAML block scalars (http://reviews.llvm.org/D9503), as the
method that parses a block scalar reuses the 'skipComment' method.

llvm-svn: 236663
2015-05-06 23:00:45 +00:00
Pete Cooper cc151ccdcf Remove unnecessary #ifndef NDEBUG guard around assert. NFC.
Found by Hal Finkel in the review of AttributeSets.  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150504/275058.html

llvm-svn: 236662
2015-05-06 22:55:46 +00:00
Duncan P. N. Exon Smith 538ef562bd Bitcode: Set LastDL after writing DebugLocs
Somehow I dropped this in r233585, and we haven't had `DEBUG_LOC_AGAIN`
records since.  Add it back.  Also tests that the output assembly looks
okay.

Fixes PR23436.

llvm-svn: 236661
2015-05-06 22:51:12 +00:00
Pete Cooper 27483915e8 Handle dead defs in the if converter.
We had code such as this:
  r2 = ...
  t2Bcc

label1:
  ldr ... r2

label2;
  return r2<dead, def>

The if converter was transforming this to
   r2<def> = ...
   return [pred] r2<dead,def>
   ldr <r2, kill>
   return

which fails the machine verifier because the ldr now reads from a dead def.

The fix here detects dead defs in stepForward and passes them back to the caller in the clobbers list.  The caller then clears the dead flag from the def is the value is live.

llvm-svn: 236660
2015-05-06 22:51:04 +00:00
Kostya Serebryany 3befe94acb [lib/Fuzzer] remove dfsan_fuzzer_abi.list -- its contents are now moved to dfsan proper
llvm-svn: 236659
2015-05-06 22:47:24 +00:00
Quentin Colombet 0ddd315db0 [RegisterCoalescer] Make sure each live-range has only one component, as
demanded by the machine verifier.
After shrinking a live-range to its uses, it is possible to create several
smaller live-ranges. When this happens, shrinkToUses returns true and we need to
split the different components into their own live-ranges.

The problem does not reproduce on any in-tree target but Jonas Paulsson
<jonas.paulsson@ericsson.com>, who reported the problem, checked that this patch
fixes the issue.

llvm-svn: 236658
2015-05-06 22:41:50 +00:00
Kostya Serebryany 754f55d6f5 [lib/Fuzzer] add a fuzzer test for memcmp (does not work yet)
llvm-svn: 236656
2015-05-06 22:36:00 +00:00
Zachary Turner 6d6e947916 Fix link failure on MinGW due to use of CoInitialize.
ole32 is considered a default library with MSVC, but apparently
not with MinGW.  Since we use CoInitialize, we need to explicitly
link against it in LLVMSupport for a MinGW build.

llvm-svn: 236654
2015-05-06 22:26:51 +00:00
Zachary Turner c007aa41b6 A few fixes for llvm-symbolizer on Windows.
Specifically, this patch correctly respects the -demangle option,
and additionally adds a hidden --relative-address option allows
input addresses to be relative to the module load address instead
of absolute addresses into the image.

llvm-svn: 236653
2015-05-06 22:26:30 +00:00
Kostya Serebryany 566bc5aa8a [lib/Fuzzer] rename TestOneInput to LLVMFuzzerTestOneInput to make it more unique
llvm-svn: 236652
2015-05-06 22:19:00 +00:00
Pete Cooper 54085cdc7b Fix incorrect kill flags in fastisel.
If called twice in the same BB on the same constant, FastISel::fastEmit_ri_ was marking the materialized vreg as killed on each use, instead of only the last use.

Change this to only mark the last use as killed by making earlier uses check if the vreg is already used elsewhere.

llvm-svn: 236650
2015-05-06 22:09:29 +00:00
Pete Cooper d31583ddfb [x86] Fix register class of folded load index reg.
When folding a load in to another instruction, we need to fix the class of the index register
Otherwise, it could be something like GR64 not GR64_NOSP and would fail the machine verifier.

llvm-svn: 236644
2015-05-06 21:37:19 +00:00
Alexey Samsonov 0a648a4bfe [SanitizerCoverage] Fix a couple of typos. NFC.
llvm-svn: 236643
2015-05-06 21:35:25 +00:00
Duncan P. N. Exon Smith c177fec93f MC: Skip names of temporary symbols in object streamer
Don't create names for temporary symbols when using an object streamer.
The names never make it to the output anyway.  From the starting point
of r236629, my heap profile says this drops peak memory usage from 1100
MB to 1058 MB for CodeGen of `verify-uselistorder`, a savings of almost
4% on peak memory, and removes `StringMap<bool, BumpPtrAllocator...>`
from the profile entirely.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)

llvm-svn: 236642
2015-05-06 21:34:34 +00:00
Tim Northover e4310fe946 CodeGen: move over-zealous assert into actual if statement.
It's quite possible to encounter an insertvalue instruction that's more deeply
nested than the value we're looking for, but when that happens we really
mustn't compare beyond the end of the index array.

Since I couldn't see any guarantees about what comparisons std::equal makes, we
probably need to directly check the size beforehand. In practice, I suspect
most std::equal implementations would probably bail early, which would be OK.
But just in case...

rdar://20834485

llvm-svn: 236635
2015-05-06 20:07:38 +00:00
Duncan P. N. Exon Smith 653c1099b4 DwarfDebug: Emit number of bytes in .debug_loc entry directly
Emit the number of bytes in a `.debug_loc` entry directly.  The old code
created temp labels (expensive), emitted the difference between them,
and then emitted one on each side of the relevant bytes.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`
(the optimized version of ld64's `-save-temps` when linking the
`verify-uselistorder` executable in an LTO bootstrap).  I've hacked
`MCContext::Allocate()` to just call `malloc()` instead of using the
`BumpPtrAllocator` so that the heap profile is easier to read.  As far
as peak memory is concerned, `MCContext::Allocate()` is equivalent to a
leak, since it only gets freed at process teardown.

In my heap profile, this patch drops memory usage of
`DwarfDebug::emitDebugLoc()` from 132.56 MB (11.4%) down to 29.86 MB
(2.7%) at peak memory.  Some of that must be noise from `SmallVector`
(or other) allocations -- peak memory only dropped from 1160 MB down to
1100 MB -- but this nevertheless shaves 5% off the top.)

llvm-svn: 236629
2015-05-06 19:11:20 +00:00
Ismail Pazarbasi 56ccf1c9d5 Implement `createSanitizerCtor`, common helper function for all sanitizers
Summary:
This helper function creates a ctor function, which calls sanitizer's
init function with given arguments. This constructor is then expected
to be added to module's ctors. The patch helps unifying how sanitizer
constructor functions are created, and how init functions are called
across all sanitizers.

Reviewers: kcc, samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8777

llvm-svn: 236627
2015-05-06 18:48:22 +00:00
Reid Kleckner d1b38c4b0b [WinEH] Improve fatal error message about failed demotion
llvm-svn: 236626
2015-05-06 18:45:24 +00:00
Sanjoy Das 6c0fe24bd1 [SelectionDAG] Delete SelectionDAGBuilder::removeValue. NFC.
SelectionDAGBuilder::removeValue is dead now, after rL236563.

llvm-svn: 236618
2015-05-06 18:02:10 +00:00
Diego Novillo 14f94de1ee Allow 0-weight branches in BranchProbabilityInfo.
Summary:
When computing branch weights in BPI, we used to disallow branches with
weight 0. This is a minor nuisance, because a branch with weight 0 is
different to "don't have information". In the context of
instrumentation, it may mean "never executed", in the context of
sampling, it means "never or seldom executed".

In allowing 0 weight branches, I ran into issues with the switch
expansion code in selection DAG. It is currently hardwired to not handle
branches with weight 0. To maintain the current behaviour, I changed it
to use 1 when it finds 0, but perhaps the algorithm needs changes to
tolerate branches with weight zero.

Reviewers: hansw

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9533

llvm-svn: 236617
2015-05-06 17:55:11 +00:00
Sanjoy Das 06cf33fbea Add missing dereferenceable_or_null getters
Summary: Add missing dereferenceable_or_null getters required for
http://reviews.llvm.org/D9253 change. Separated from the D9253 review.

Patch by Artur Pilipenko!

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9499

llvm-svn: 236615
2015-05-06 17:41:54 +00:00
Wei Mi 062c74484d [X86] Disable loop unrolling in loop vectorization pass when VF is 1.
The patch disabled unrolling in loop vectorization pass when VF==1 on x86 architecture,
by setting MaxInterleaveFactor to 1. Unrolling in loop vectorization pass may introduce
the cost of overflow check, memory boundary check and extra prologue/epilogue code when
regular unroller will unroll the loop another time. Disable it when VF==1 remove the
unnecessary cost on x86. The same can be done for other platforms after verifying
interleaving/memory bound checking to be not perf critical on those platforms.

Differential Revision: http://reviews.llvm.org/D9515

llvm-svn: 236613
2015-05-06 17:12:25 +00:00
Matt Arsenault 633dba4f41 Add ChangeTo* to MachineOperand for symbols
llvm-svn: 236612
2015-05-06 17:05:54 +00:00
Derek Schuff 5d8dfd39e1 Add bitcode test to verify functions can be materialized out of order.
Summary:
Adds test to check that when getLazyBitcodeModule is called:
1) Functions are not materailzed by default.
2) Only the requested function gets materialized (if no block addresses
   are used).

Reviewers: jvoung, rafael

Reviewed By: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8907

llvm-svn: 236611
2015-05-06 16:52:35 +00:00
Pawel Bylica 3b0adaf6b0 Readd the regression test from r236584. Calling convention fixed to linux.
llvm-svn: 236610
2015-05-06 16:43:21 +00:00
Pete Cooper d927c6eaf8 [ARM] Fast-Isel was incorrectly selecting <2 x double> adds.
With neon enabled, we reach SelectBinaryFPOp and are able to get registers for a <2 x double> add.

However, we shouldn't actually attempt arithmetic on it as ARMIselLowering says "v2f64 is legal so that QR subregs can be extracted as f64 elements, but neither Neon nor VFP support any arithmetic operations on it."

This commit disables SelectBinaryFPOp for any vector types.  There's already a FIXME to try handle neon.  Doing so would require fixing this conditional which isn't safe for vectors 'VT == MVT::f64 || VT == MVT::i64'

llvm-svn: 236609
2015-05-06 16:39:17 +00:00
Bill Schmidt 5fe2e25f7c [PPC64LE] Adjust vector splats during VSX swap optimization
The initial code drop for VSX swap optimization permitted the
optimization only when all operations in a web of related computation
are lane-insensitive.  For some lane-sensitive operations, we can
still permit the optimization provided that we make adjustments to
those operations.  This patch adds special handling for vector splats
so that their presence doesn't kill the optimization.

Vector splats are lane-sensitive since they identify by number a
vector element to be used as the source of a splat.  When swap
optimizations take place, the desired vector element will move to the
opposite doubleword of the quadword vector.  We thus replace the index
I by (I + N/2) % N, where N is the number of elements in the vector.

A new test case is added to test that swap optimization succeeds when
vector splats are present, and that the proper input element is used
as the source of the splat.

An ancillary change removes SH_BUILDVEC as one of the kinds of special
handling that may be required by VSX swap optimization.  From
experience with GCC, I had expected to need some modifications for
vector build operations, but I did not find that to be the case.

llvm-svn: 236606
2015-05-06 15:40:46 +00:00
NAKAMURA Takumi e452998b4b Reformat.
llvm-svn: 236601
2015-05-06 14:03:22 +00:00
NAKAMURA Takumi d7c0be9c42 Revert r236546, "propagate IR-level fast-math-flags to DAG nodes (NFC)"
It caused undefined behavior.

llvm-svn: 236600
2015-05-06 14:03:12 +00:00
Artyom Skrobov 3f8eae92a4 [ARM] generate VMAXNM/VMINNM for a compare followed by a select, in safe math mode too
llvm-svn: 236590
2015-05-06 11:44:10 +00:00
Pawel Bylica b25491faf4 Revert regression test from r236584.
Temporary remove a regression test added in r236584. It fails on Windows.

llvm-svn: 236586
2015-05-06 10:41:46 +00:00
Pawel Bylica 9f1fb9d1ef SelectionDAG: Handle out-of-bounds index in extract vector element
Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size.

Test Plan:
CodeGen for X86 test included.
Also one incorrect regression test fixed.

Reviewers: qcolombet, chandlerc, hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D9250

llvm-svn: 236584
2015-05-06 10:19:14 +00:00
Adam Nemet e340f851a3 [DomTree] verifyDomTree to unconditionally perform DT verification
I folded the check for the flag -verify-dom-info into the only caller
where I think it is supposed to be checked: verifyAnalysis.  (The idea
of the flag is to enable this expensive verification in
verifyPreservedAnalysis.)

I'm assuming that when manually scheduling the verification pass
with -passes=verify<domtree>, we do want to perform the verification.

llvm-svn: 236575
2015-05-06 08:18:41 +00:00
Ahmed Bougacha e8d0c4ccea [ARM][FastISel] Use TST #1 instead of CMP #0 for select.
Since r234249, i1 are sext instead of zext; because of that, doing
"CMP rN, #0; IT EQ/NE" isn't correct anymore.

"TST #1" is the conservatively correct alternative - the tradeoff being
that it doesn't have a 16-bit encoding -, so use that instead.

llvm-svn: 236569
2015-05-06 04:14:02 +00:00
Sanjoy Das 77b16b78e9 [Statepoints] Remove broken test case.
statepoint-indirect-return.ll breaks on linux systems.  Delete the test
case to make the bots green while I figure out what the right fix is.

llvm-svn: 236568
2015-05-06 02:51:46 +00:00
Sanjoy Das 63245b5d3c [IRBuilder] Fix indentation. NFC.
Whitespace-only change.

llvm-svn: 236567
2015-05-06 02:36:34 +00:00
Sanjoy Das 4bfb472072 [Statepoint] Clean up StatepointLowering: symbolic constants.
For accessors in the `Statepoint` class, use symbolic constants for
offsets into the argument vector instead of literals.  This makes the
code intent clearer and simpler to change.

llvm-svn: 236566
2015-05-06 02:36:31 +00:00
Sanjoy Das b023d06bb0 [Statepoint] Clean up Statepoint.h: clang-format.
llvm-svn: 236565
2015-05-06 02:36:28 +00:00
Sanjoy Das 499d703f52 [Statepoint] Clean up Statepoint.h: accessor names.
Use getFoo() as accessors consistently and some other naming changes.

llvm-svn: 236564
2015-05-06 02:36:26 +00:00
Sanjoy Das c6bf3e9f12 [StatepointLowering] Don't create temporary instructions. NFCI.
Summary:
Instead of creating a temporary call instruction and lowering that, use
SelectionDAGBuilder::lowerCallOperands.

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9480

llvm-svn: 236563
2015-05-06 02:36:20 +00:00
Ahmed Bougacha ed363c5dcb [WinEH] Reset WinEHPrepare::SEHExceptionCodeSlot when we're done.
This caused a use-after-free on test/CodeGen/X86/win32-eh.ll
No functional change intended.

llvm-svn: 236561
2015-05-06 01:28:58 +00:00
Justin Bogner 0b4c484fb9 InstrProf: Strip filename prefixes from the names we display for coverage
For consumers of coverage data, any filename prefixes we store in the
profile data are just noise. Strip this prefix if it exists.

llvm-svn: 236558
2015-05-05 23:44:48 +00:00
Pete Cooper d0dae3e577 [X86 fast-isel] Constrain the index reg class to not include SP.
The index reg on instructions with complex address modes is a GPR64_NOSP.  Constrain it to appease the machine verifier.

llvm-svn: 236557
2015-05-05 23:41:53 +00:00
Sanjoy Das 1194d1e799 [SelectionDAG] Make an argument optional in RFV::getCopyToRegs. NFC.
Summary:
We default the value argument to nullptr.  The only use of the value is
in diagnosePossiblyInvalidConstraint and that seems to be resilient to
it being nullptr.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9479

llvm-svn: 236555
2015-05-05 23:06:57 +00:00
Sanjoy Das 3936a97f11 [SelectionDAG] Move RegsForValue into SelectionDAGBuilder.h. NFC.
Summary:
The exported class will be used in later change, in
StatepointLowering.cpp.  It is still internal to SelectionDAG (not
exported via include/).

Reviewers: reames, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9478

llvm-svn: 236554
2015-05-05 23:06:54 +00:00
Sanjoy Das 84153c450a [SelectionDAG] Pass explicit type to lowerCallOperands. NFC.
Summary:
Currently this does not change anything, but change will be used in a
later change to StatepointLowering.cpp

Reviewers: reames, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9477

llvm-svn: 236553
2015-05-05 23:06:52 +00:00
Sanjoy Das 3fb91c0a0d [StatepointLowering] Rename variable, NFC.
Rename LoweredArgs to LoweredMetaArgs to clarify intent.

llvm-svn: 236552
2015-05-05 23:06:49 +00:00
Pete Cooper ce9ad757c7 Fix IfConverter to handle regmask machine operands.
Note, this is a recommit of r236515 after fixing an error in r236514.  The buildbot ran fast enough that it picked up r236514 prior to r236515 and threw an error.  r236515 itself ran 'make check' without errors.

Original commit message follows:

A regmask (typically seen on a call) clobbers the set of registers it lists.  The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks.

These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier.  Otherwise, uses after the if converted call could think they are reading an undefined register.

Reviewed by Matthias Braun and Quentin Colombet.

llvm-svn: 236550
2015-05-05 22:09:41 +00:00
Kostya Serebryany ca6a2a2f1c [lib/Fuzzer] on crash print the contents of the crashy input as base64
llvm-svn: 236548
2015-05-05 21:59:51 +00:00
Sanjay Patel 801caff64d propagate IR-level fast-math-flags to DAG nodes (NFC)
This patch adds the minimum plumbing necessary to use IR-level
fast-math-flags (FMF) in the backend without actually using
them for anything yet. This is a follow-on to:
http://reviews.llvm.org/rL235997

...which split the existing nsw / nuw / exact flags and FMF
into their own struct.

There are 2 structural changes here:

1. The main diff is that we're preparing to extend the optimization
flags to affect more than just binary SDNodes. Eg, IR intrinsics 
( https://llvm.org/bugs/show_bug.cgi?id=21290 ) or non-binop nodes
that don't even exist in IR such as FMA, FNEG, etc.

2. The other change is that we're actually copying the FP fast-math-flags
from the IR instructions to SDNodes. 

Differential Revision: http://reviews.llvm.org/D8900

llvm-svn: 236546
2015-05-05 21:40:38 +00:00
Sanjay Patel fbca70d767 use range-based for-loop; NFC
llvm-svn: 236544
2015-05-05 21:20:52 +00:00
Andrey Churbanov 7ecb0714be Added Andrey Churbanov as the owner of the OpenMP runtime library code
llvm-svn: 236540
2015-05-05 20:17:53 +00:00
David Majnemer ac256cfed2 [Inliner] Discard empty COMDAT groups
COMDAT groups which have become rendered unused because of inline are
discardable if we can prove that we've made the group empty.

This fixes PR22285.

llvm-svn: 236539
2015-05-05 20:14:22 +00:00
Pete Cooper 7605e37a63 Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC
Note, this is a reapplication of r236515 with a fix to not assert on non-register operands, but instead only handle them until the subsequent commit.  Original commit message follows.

The code was basically the same here already.  Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs.

Will be used in the next commit to also handle regmasks.

llvm-svn: 236538
2015-05-05 20:14:22 +00:00
Peter Collingbourne 85a0e23bc8 Thumb2SizeReduction: Check the correct set of registers for LDMIA.
The register set for LDMIA begins at offset 3, not 4. We were previously
missing the short encoding of this instruction in the case where the base
register was the first register in the register set.

Also clean up some dead code:

- The isARMLowRegister check is redundant with what VerifyLowRegs does;
  replace with an assert.
- Remove handling of LDMDB instruction, which has no short encoding (and
  does not appear in ReduceTable).

Differential Revision: http://reviews.llvm.org/D9485

llvm-svn: 236535
2015-05-05 20:07:10 +00:00
Ulrich Weigand 9958c489bb [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load
This patch makes ReplaceExtractVectorEltOfLoadWithNarrowedLoad convert
the element number from getVectorIdxTy() to PtrTy before doing pointer
arithmetic on it.  This is needed on z, where element numbers are i32
but pointers are i64.

Original patch by Richard Sandiford.

llvm-svn: 236530
2015-05-05 19:34:10 +00:00
Ulrich Weigand af2c618e2b [DAGCombiner] Fix ReplaceExtractVectorEltOfLoadWithNarrowedLoad for BE
For little-endian, the function would convert (extract_vector_elt (load X), Y)
to X + Y*sizeof(elt).  For big-endian it would instead use
X + sizeof(vec) - Y*sizeof(elt).  The big-endian case wasn't right since
vector index order always follows memory/array order, even for big-endian.
(Note that the current handling has to be wrong for Y==0 since it would
access beyond the end of the vector.)

Original patch by Richard Sandiford.

llvm-svn: 236529
2015-05-05 19:33:37 +00:00
Ulrich Weigand 2693c0a491 [LegalizeVectorTypes] Allow single loads and stores for more short vectors
When lowering a load or store for TypeWidenVector, the type legalizer
would use a single load or store if the associated integer type was legal.
E.g. it would load a v4i8 as an i32 if i32 was legal.

This patch extends that behavior to promoted integers as well as legal ones.
If the integer type for the full vector width is TypePromoteInteger,
the element type is going to be TypePromoteInteger too, and it's still
better to use a single promoting load or truncating store rather than N
individual promoting loads or truncating stores.  E.g. if you have a v2i8
on a target where i16 is promoted to i32, it's better to load the v2i8 as
an i16 rather than load both i8s individually.

Original patch by Richard Sandiford.

llvm-svn: 236528
2015-05-05 19:32:57 +00:00
Ulrich Weigand c1708b2618 [SystemZ] Add vector intrinsics
This adds intrinsics to allow access to all of the z13 vector instructions.
Note that instructions whose semantics can be described by standard LLVM IR
do not get any intrinsics.

For each instructions whose semantics *cannot* (fully) be described, we
define an LLVM IR target-specific intrinsic that directly maps to this
instruction.

For instructions that also set the condition code, the LLVM IR intrinsic
returns the post-instruction CC value as a second result.  Instruction
selection will attempt to detect code that compares that CC value against
constants and use the condition code directly instead.

Based on a patch by Richard Sandiford.

llvm-svn: 236527
2015-05-05 19:31:09 +00:00
Ulrich Weigand 5211f9ff4d [SystemZ] Mark v1i128 and v1f128 as unsupported
The ABI specifies that <1 x i128> and <1 x fp128> are supposed to be
passed in vector registers.  We do not yet support those types, and
some infrastructure is missing before we can do so.

In order to prevent accidentally generating code violating the ABI,
this patch adds checks to detect those types and error out if user
code attempts to use them.

llvm-svn: 236526
2015-05-05 19:30:05 +00:00
Ulrich Weigand cd2a1b5341 [SystemZ] Handle sub-128 vectors
The ABI allows sub-128 vectors to be passed and returned in registers,
with the vector occupying the upper part of a register.  We therefore
want to legalize those types by widening the vector rather than promoting
the elements.

The patch includes some simple tests for sub-128 vectors and also tests
that we can recognize various pack sequences, some of which use sub-128
vectors as temporary results.  One of these forms is based on the pack
sequences generated by llvmpipe when no intrinsics are used.

Signed unpacks are recognized as BUILD_VECTORs whose elements are
individually sign-extended.  Unsigned unpacks can have the equivalent
form with zero extension, but they also occur as shuffles in which some
elements are zero.

Based on a patch by Richard Sandiford.

llvm-svn: 236525
2015-05-05 19:29:21 +00:00
Ulrich Weigand 49506d78e7 [SystemZ] Add CodeGen support for scalar f64 ops in vector registers
The z13 vector facility includes some instructions that operate only on the
high f64 in a v2f64, effectively extending the FP register set from 16
to 32 registers.  It's still better to use the old instructions if the
operands happen to fit though, since the older instructions have a shorter
encoding.

Based on a patch by Richard Sandiford.

llvm-svn: 236524
2015-05-05 19:28:34 +00:00
Ulrich Weigand 80b3af7ab3 [SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used.  Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.

This particularly helps with llvmpipe.

Based on a patch by Richard Sandiford.

llvm-svn: 236523
2015-05-05 19:27:45 +00:00
Ulrich Weigand cd808237b2 [SystemZ] Add CodeGen support for v2f64
This adds ABI and CodeGen support for the v2f64 type, which is natively
supported by z13 instructions.

Based on a patch by Richard Sandiford.

llvm-svn: 236522
2015-05-05 19:26:48 +00:00
Ulrich Weigand ce4c109585 [SystemZ] Add CodeGen support for integer vector types
This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility.  This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).

When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
  (except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.

The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.

However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.

These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level.  This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.

Based on a patch by Richard Sandiford.

llvm-svn: 236521
2015-05-05 19:25:42 +00:00
Ulrich Weigand a8b04e1cbc [SystemZ] Add z13 vector facility and MC support
This patch adds support for the z13 processor type and its vector facility,
and adds MC support for all new instructions provided by that facilily.

Apart from defining the new instructions, the main changes are:

- Adding VR128, VR64 and VR32 register classes.
- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.
- Adding a D(V,B) addressing mode for scatter/gather operations
- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields.
  Until now all immediate operands have been the same width as the
  underlying field (hence the assert->return change in decode[SU]ImmOperand).

In addition, sys::getHostCPUName is extended to detect running natively
on a z13 machine.

Based on a patch by Richard Sandiford.

llvm-svn: 236520
2015-05-05 19:23:40 +00:00
Pete Cooper 336d90b61b Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"
This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514)

This is to get the bots green while i investigate.

llvm-svn: 236518
2015-05-05 18:49:08 +00:00
Pete Cooper 05b84d4168 Revert "Fix IfConverter to handle regmask machine operands."
This reverts commit b27413cbfd78d959c18e713bfa271fb69e6b3303 (ie r236515).

This is to get the bots green while i investigate the failures.

llvm-svn: 236517
2015-05-05 18:49:05 +00:00
Pete Cooper 6ebc207703 Fix IfConverter to handle regmask machine operands.
A regmask (typically seen on a call) clobbers the set of registers it lists.  The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks.

These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier.  Otherwise, uses after the if converted call could think they are reading an undefined register.

Reviewed by Matthias Braun and Quentin Colombet.

llvm-svn: 236515
2015-05-05 18:31:36 +00:00
Pete Cooper bbd1c727d1 Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC
The code was basically the same here already.  Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs.

Will be used in the next commit to also handle regmasks.

llvm-svn: 236514
2015-05-05 18:31:31 +00:00
Diego Novillo 32a0bee2bb Fix typo in assert message. NFC.
llvm-svn: 236513
2015-05-05 18:24:47 +00:00
David Blaikie b10516e4ba Fix the clang -Werror build, use of uninitialized variable.
llvm-svn: 236512
2015-05-05 18:12:33 +00:00
Daniel Berlin 3459d6ead5 Update BasicAliasAnalysis to understand that nothing aliases with undef values.
It got this in some cases (if one of them was an identified object), but not in all cases.

This caused stores to undef to block load-forwarding in some cases, etc.

Added test to Transforms/GVN to verify optimization occurs as expected.

llvm-svn: 236511
2015-05-05 18:10:49 +00:00
David Blaikie 73cf872adb [opaque pointer type] Track explicit GEP pointee type through in-memory IR
llvm-svn: 236510
2015-05-05 18:03:48 +00:00
Reid Kleckner 0738a9c02e Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236360.

This change exposed a bug in WinEHPrepare by opting win32 code into EH
preparation. We already knew that WinEHPrepare has bugs, and is the
status quo for x64, so I don't think that's a reason to hold off on this
change. I disabled exceptions in the sanitizer tests in r236505 and an
earlier revision.

llvm-svn: 236508
2015-05-05 17:44:16 +00:00
Quentin Colombet 61b305edfd [ShrinkWrap] Add (a simplified version) of shrink-wrapping.
This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits
blocks.

As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.


** Context **

Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
places.
The job of the shrink-wrapping pass is to identify such places.


** Motivating example **

Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b)  {
 %tmp = alloca i32, align 4
 %tmp2 = icmp slt i32 %a, %b
 br i1 %tmp2, label %true, label %false

true:
 store i32 %a, i32* %tmp, align 4
 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
 br label %false

false:
 %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
 ret i32 %tmp.0
}

On AArch64 this code generates (removing the cfi directives to ease
readabilities):
_f:                                     ; @f
; BB#0:
  stp x29, x30, [sp, #-16]!
  mov  x29, sp
  sub sp, sp, #16             ; =16
  cmp  w0, w1
  b.ge  LBB0_2
; BB#1:                                 ; %true
  stur  w0, [x29, #-4]
  sub x1, x29, #4             ; =4
  mov  w0, wzr
  bl  _doSomething
LBB0_2:                                 ; %false
  mov  sp, x29
  ldp x29, x30, [sp], #16
  ret

With shrink-wrapping we could generate:
_f:                                     ; @f
; BB#0:
  cmp  w0, w1
  b.ge  LBB0_2
; BB#1:                                 ; %true
  stp x29, x30, [sp, #-16]!
  mov  x29, sp
  sub sp, sp, #16             ; =16
  stur  w0, [x29, #-4]
  sub x1, x29, #4             ; =4
  mov  w0, wzr
  bl  _doSomething
  add sp, x29, #16            ; =16
  ldp x29, x30, [sp], #16
LBB0_2:                                 ; %false
  ret

Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.


** Proposed Solution **

This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.

Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.

The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using
-enable-shrink-wrap.

Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.


** Design Decisions **

1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
  pointer.
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating
examples.

Differential Revision: http://reviews.llvm.org/D9210

<rdar://problem/3201744>

llvm-svn: 236507
2015-05-05 17:38:16 +00:00
Lang Hames cd68eba3b9 [Orc] Reapply r236465 with fixes for the MSVC bots.
llvm-svn: 236506
2015-05-05 17:37:18 +00:00
Daniel Sanders 85202063c0 [bugpoint] Increase default memory limit to 400MB to fix bugpoint tests.
I tracked down the bug to an unchecked malloc in SmallVectorBase::grow_pod().
This malloc is returning NULL on my machine when running under bugpoint but not
when -enable-valgrind is given.

llvm-svn: 236504
2015-05-05 16:29:40 +00:00
Kit Barton d4eb73c00e This patch adds ABI support for v1i128 data type.
It adds v1i128 to the appropriate register classes and checks parameter passing
and return values.

This is related to http://reviews.llvm.org/D9081, which will add instructions
that exploit the v1i128 datatype.

Phabricator review: http://reviews.llvm.org/D9475

llvm-svn: 236503
2015-05-05 16:10:44 +00:00
Igor Laevsky 2aa8cafaf6 Emit comment for gc.relocate showing base and derived pointers in human readable form.
Differential Revision: http://reviews.llvm.org/D9326

llvm-svn: 236497
2015-05-05 13:20:42 +00:00
Daniel Sanders eda60d217b [mips] Generate code for insert/extract operations when using the N64 ABI and MSA.
Summary:
When using the N64 ABI, element-indices use the i64 type instead of i32.
In many cases, we can use iPTR to account for this but additional patterns
and pseudo's are also required.

This fixes most (but not quite all) failures in the test-suite when using
N64 and MSA together.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9342

llvm-svn: 236494
2015-05-05 10:32:24 +00:00
Ismail Donmez 5eb52b74cb Fix regression in parsing armv{6,7}hl- triples. These are used by SUSE
and Redhat currently.

Reviewed by Jonathan Roelofs.

llvm-svn: 236492
2015-05-05 09:29:43 +00:00
Daniel Sanders 4160c802d9 [mips][msa] Test basic operations for the N32 ABI too.
Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341

llvm-svn: 236489
2015-05-05 08:48:35 +00:00
Kostya Serebryany 177582c90f [lib/Fuzzer] use handle_abort=1 by default so that when assert() fires we save the test case
llvm-svn: 236476
2015-05-05 01:42:55 +00:00
Lang Hames ac31a1f141 [Orc] Revert r236465 - It broke the Windows bots.
Looks like the usual missing explicit move-constructor issue with MSVC. I should
have a fix shortly.

llvm-svn: 236472
2015-05-04 23:30:01 +00:00
Reid Kleckner 9dad227b85 [X86] Fix assertion while DAG combining offsets and ExternalSymbols
ExternalSymbol nodes do not contain offsets, unlike GlobalValue nodes.

llvm-svn: 236471
2015-05-04 23:22:36 +00:00
Pete Cooper 4dddbcfbb1 [ARM] IT block insertion needs to update kill flags
When forming an IT block from the first MOV here:

	%R2<def> = t2MOVr %R0, pred:1, pred:%CPSR, opt:%noreg
	%R3<def> = tMOVr %R0<kill>, pred:14, pred:%noreg

the move in to R3 is moved out of the IT block so that later instructions on the same predicate can be inside this block, and we can share the IT instruction.

However, when moving the R3 copy out of the IT block, we need to clear its kill flags for anything in use at this point in time, ie, R0 here.

This appeases the machine verifier which thought that R0 wasn't defined when used.

I have a test case, but its extremely register allocator specific.  It would be too fragile to commit a test which depends on the register allocator here.

llvm-svn: 236468
2015-05-04 22:44:47 +00:00
Pete Cooper b5445cce73 Add TransformUtils dependency to lli.
After r236465, Orc uses ValueMaterializer and so needs to link against TransformUtils to get the ValueMaterializer::anchor().

llvm-svn: 236467
2015-05-04 22:33:39 +00:00
Lang Hames a68970dfd5 [Orc] Refactor the compile-on-demand layer to make module partitioning lazy,
and avoid cloning unused decls into every partition.

Module partitioning showed up as a source of significant overhead when I
profiled some trivial test cases. Avoiding the overhead of partitionging
for uncalled functions helps to mitigate this.

This change also means that it is no longer necessary to have a
LazyEmittingLayer underneath the CompileOnDemand layer, since the
CompileOnDemandLayer will not extract or emit function bodies until they are
called.

llvm-svn: 236465
2015-05-04 22:03:10 +00:00
Matthias Braun 19ffc26c5e Vim: Fix some bugs in llvm indent plugin.
llvm-svn: 236464
2015-05-04 21:41:25 +00:00
Matthias Braun 825b32acb4 Vim: Set filetype=python for lit configuration files.
llvm-svn: 236463
2015-05-04 21:41:23 +00:00
Matthias Braun 29f3f1163f Document some of the options in test/lit.cfg
llvm-svn: 236462
2015-05-04 21:37:00 +00:00
Matthias Braun 219144e6a7 Lit: Allow overriding llvm tool paths+arguments, make -D an alias for --param
These changes allow usages where you want to pass an additional
commandline option to all invocations of a specific llvm tool. Example:

> llvm-lit -Dllc=llc -enable-misched -verify-machineinstrs

Differential Revision: http://reviews.llvm.org/D9487

llvm-svn: 236461
2015-05-04 21:36:36 +00:00
Sanjay Patel ec2d7358b9 zap windows line endings; NFC
llvm-svn: 236460
2015-05-04 21:27:27 +00:00
Tim Northover 851ff69b42 CodeGen: match up correct insertvalue indices when assessing tail calls.
When deciding whether a value comes from the aggregate or inserted value of an
insertvalue instruction, we compare the indices against those of the location
we're interested in. One of the lists needs reversing because the input data is
backwards (so that modifications take place at the end of the SmallVector), but
we were reversing both before leading to incorrect results.

Should fix PR23408

llvm-svn: 236457
2015-05-04 20:41:51 +00:00
Alex Lorenz b122508501 YAML: Add an optional 'flow' field to the mapping trait to allow flow mapping output.
This patch adds an optional 'flow' field to the MappingTrait
class so that yaml IO will be able to output flow mappings.

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9450

llvm-svn: 236456
2015-05-04 20:11:40 +00:00
Keno Fischer d71a17710b Respect object format choice on Darwin
Summary:
The object format can be set to something other than MachO, e.g.
to use ELF-on-Darwin for MCJIT. This already works on Windows, so
there's no reason it shouldn't on Darwin.

Reviewers: lhames, grosbach

Subscribers: rafael, grosbach, t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D6185

llvm-svn: 236455
2015-05-04 20:03:01 +00:00
Reid Kleckner b61f06c9c2 Fix -Wmicrosoft warning by making enum unsigned
llvm-svn: 236436
2015-05-04 18:21:35 +00:00
Davide Italiano e197d4fbb6 [IR/Diagnostic] Assert that DebugLoc is valid before accessing.
PR:		23380
Differential Revision:	http://reviews.llvm.org/D9464
Reviewed by:	dexonsmith

llvm-svn: 236435
2015-05-04 18:08:35 +00:00
Hans Wennborg 8d8146fa73 Option parsing: properly handle flag aliases for joined options (PR23394)
A joined option always needs to have an argument, even if it's an empty one.

Clang would previously assert when trying to use --extra-warnings, which is
a flag alias for -W, which is a joined option.

llvm-svn: 236434
2015-05-04 18:00:13 +00:00
Ulrich Weigand 9ac2f9b2d8 [SystemZ] Reclassify f32 subregs of f64 registers
At the moment, all subregs defined by the SystemZ target can be modified
independently of the wider register.  E.g. writing to a GR32 does not
change the upper 32 bits of the GR64.  Writing to an FP32 does not change
the lower 32 bits of the FP64.

Hoewver, the upcoming support for the vector extension redefines FP64 as
one half of a V128.  Floating-point operations leave the other half of
a V128 in an unpredictable state, so it's no longer the case that writing
to an FP32 leaves the bits of the underlying register (the V128) alone.
I'd prefer to have separate subreg_ names for this situation, so that
it's obvious at a glance whether we're talking about a subreg that leaves
the other parts of the register alone.

No behavioral change intended.

Patch originally by Richard Sandiford.

llvm-svn: 236433
2015-05-04 17:41:22 +00:00
Ulrich Weigand 1f698b003c [SystemZ] Clean up AsmParser isMem() handling
We know what MemoryKind an operand has at the time we construct it,
so we might as well just record it in an unused part of the structure.
This makes it easier to add scatter/gather addresses later.

No behavioral change intended.

Patch originally by Richard Sandiford.

llvm-svn: 236432
2015-05-04 17:40:53 +00:00
Ulrich Weigand 1c6f07d616 [SystemZ] Fix getTargetNodeName
It seems SystemZTargetLowering::getTargetNodeName got out of sync with
some recent changes to the SystemZISD opcode list.  Add back all the
missing opcodes (and re-sort to the same order as SystemISelLowering.h).

llvm-svn: 236430
2015-05-04 17:39:40 +00:00
Pete Cooper 300069a019 ScheduleDAGInstrs should toggle kill flags on bundled instrs.
ScheduleDAGInstrs wasn't setting or clearing the kill flags on instructions inside bundles.  This led to code such as this

%R3<def> = t2ANDrr %R0
BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use,kill>
  t2IT 1, 24, %ITSTATE<imp-def>
  R6<def,tied6> = t2ORRrr %R0<kill>, ...

being transformed to

BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use>
  t2IT 1, 24, %ITSTATE<imp-def>
  R6<def,tied6> = t2ORRrr %R0<kill>, ...
%R3<def> = t2ANDrr %R0<kill>

where the kill flag was removed from the BUNDLE instruction, but not the t2ORRrr inside it.  The verifier then thought that
R0 was undefined when read by the AND.

This change make the toggleKillFlags method also check for bundles and toggle flags on bundled instructions.
Setting the kill flag is special cased as we only want to set the kill flag on the last instruction in the bundle.

llvm-svn: 236428
2015-05-04 16:52:06 +00:00
Tom Stellard b81f4aa952 R600/SI: Code cleanup
This is a follow-up to r236004

llvm-svn: 236427
2015-05-04 16:45:08 +00:00
Elena Demikhovsky d41e506342 AVX-512: added a test for encoding
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236421
2015-05-04 12:59:15 +00:00
Elena Demikhovsky 60eb9db7bb AVX-512: added calling convention for i1 vectors in 32-bit mode.
Fixed some bugs in extend/truncate for AVX-512 target.
Removed VBROADCASTM (masked broadcast) node, since it is not used any more.

llvm-svn: 236420
2015-05-04 12:40:50 +00:00
Elena Demikhovsky 52266388f8 AVX-512: added integer "add" and "sub" instructions with saturation for SKX
with intrinsics and tests

by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236418
2015-05-04 12:35:55 +00:00
Elena Demikhovsky 9ebd877a10 AVX-512: enabled tests for AVX512F set
llvm-svn: 236416
2015-05-04 11:09:41 +00:00
Elena Demikhovsky 2557a22be7 AVX-512: Added VPACK* instructions forms for KNL and SKX
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)

llvm-svn: 236414
2015-05-04 09:14:02 +00:00
Yaron Keren f8e6517591 Replace windows_error calls with mapWindowsError.
After r210687, windows_error does nothing but call mapWindowsError.
Other Windows/*.inc files directly call mapWindowsError. This patch
updates Path.inc and Process.inc to do the same.

llvm-svn: 236409
2015-05-04 04:48:10 +00:00
Justin Bogner 65337d1f3a llvm-cov: Warn if object file is newer than profile
Looking at coverage with an out of date profile can be confusing.
Provide a little hint that something might be wrong.

llvm-svn: 236408
2015-05-04 04:09:38 +00:00
Jonathan Roelofs 949d55d87a Deprecate in-source autotools builds
This is a followup from:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150323/268067.html

Upgrade instructions:
  $ mv llvm/include/llvm/Config/config.h ./config.h.BACKUP
  # copy the configure line from line 7 of llvm/config.log
  # (for example: `$ ./configure --no-create --no-recursion`)
  $ mkdir build
  $ cd build
  # run the configure line, but this time with '../llvm' at the beginning:
  $ ../llvm/configure --no-create --no-recursion

These warnings will soon be turned into hard errors after a week.  Speak up now
if this is going to be a problem for you.

llvm-svn: 236399
2015-05-04 02:04:54 +00:00
Craig Topper 23fdafe682 [TableGen] Replace 'static_cast' with 'cast'.
llvm-svn: 236398
2015-05-04 01:35:42 +00:00
Craig Topper a9642b4ec8 [TableGen] Formatting cleanup. Mostly removing trailing whitespace and unnecessary curly braces. NFC
llvm-svn: 236397
2015-05-04 01:35:39 +00:00
Elena Demikhovsky 1b60ed7069 Masked gather and scatter intrinsics - enabled codegen for KNL.
llvm-svn: 236394
2015-05-03 07:12:25 +00:00
Nico Weber 4b5b1ac997 Fix typo in comment.
llvm-svn: 236392
2015-05-02 21:34:39 +00:00
Simon Pilgrim d5e20306cc [SSE2] Minor tidyup of v16i8 SHL lowering. NFC.
Removed code that was replicating v8i16 'shift + mask' implementation that is done more nicely by making use of LowerScalarImmediateShift

llvm-svn: 236388
2015-05-02 14:42:43 +00:00
Simon Pilgrim 017ca19384 [DAGCombiner] Enabled vector float/double -> int constant folding
llvm-svn: 236387
2015-05-02 13:04:07 +00:00
Simon Pilgrim e170a4f5fa Line ending fix
llvm-svn: 236386
2015-05-02 11:50:47 +00:00
Simon Pilgrim 7d6df82dd1 [SSE] Added vector int (i32 and i64) -> float/double conversion tests
llvm-svn: 236385
2015-05-02 11:42:47 +00:00
Simon Pilgrim 6e3b7bad11 [SSE] Added vector float/double -> i32 and i64 conversion tests
llvm-svn: 236384
2015-05-02 11:18:47 +00:00
David Blaikie 72d03efa6d DebugInfo: Use low_pc relative debug_ranges under fission when the CU has a low_pc
Seems we were setting the base address on the wrong DwarfCompileUnit
object so it wasn't being used when generating the ranges.

llvm-svn: 236377
2015-05-02 02:31:49 +00:00
Eric Christopher a2d44dee73 Rework test to use FileCheck by making sure we have no xmm registers
with numbers.

llvm-svn: 236373
2015-05-02 01:06:17 +00:00
Jim Grosbach ae4c2649dc MC: Tidy up comments and clean up formatting a bit. NFC.
llvm-svn: 236368
2015-05-02 00:44:14 +00:00
Jim Grosbach bfe3a9c318 Fix spelling.
llvm-svn: 236367
2015-05-02 00:44:07 +00:00
Reid Kleckner 83d89fa546 Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236359. Things are still broken despite testing. :(

llvm-svn: 236360
2015-05-01 22:50:14 +00:00
Reid Kleckner 51476acd77 Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236340.

llvm-svn: 236359
2015-05-01 22:40:25 +00:00
Colin LeMahieu bb0d7cbee1 [Hexagon] r236351 fix does not work on builder configurations yet.
llvm-svn: 236358
2015-05-01 22:39:20 +00:00
Quentin Colombet 0de2346859 [AArch64][FastISel] Variant of the logical instructions that use two input
registers cannot write on SP.

rdar://problem/20748715

llvm-svn: 236352
2015-05-01 21:34:57 +00:00
Colin LeMahieu 6efd273a61 [Hexagon] Removing variable unused in release.
llvm-svn: 236351
2015-05-01 21:30:22 +00:00
Colin LeMahieu b662565475 [Hexagon] Adding expression MC emission and removing XFAIL from test that hits this code path.
llvm-svn: 236348
2015-05-01 21:14:21 +00:00
Quentin Colombet 9df2fa261b [AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.
rdar://problem/20748715

llvm-svn: 236346
2015-05-01 20:57:11 +00:00
Zachary Turner 292e92d99d Fix compilation of PDBApiTest.
llvm-svn: 236345
2015-05-01 20:51:49 +00:00
Zachary Turner 6799af41fe Fix build.
llvm-svn: 236343
2015-05-01 20:33:10 +00:00
Zachary Turner e5cb269352 [llvm-pdbdump] Support dynamic load address and external symbols.
This patch adds the --load-address command line option to
llvm-pdbdump, which dumps all addresses assuming the module has
loaded at the specified address.

Additionally, this patch adds an option to llvm-pdbdump to support
dumping of public symbols (i.e. symbols with external linkage).

llvm-svn: 236342
2015-05-01 20:24:26 +00:00
Keno Fischer e6892c8149 Reapply [RuntimeDyldELF] Fold Placeholder into Addend
This reapplies r235060 and 235070, which were reverted because of test failures
in LLDB. The failure was caused because at  moment RuntimeDyld is processing
relocations for all sections, irrespective of whether we actually load them
into memory or not, but RuntimeDyld was not actually remembering where in memory
the unrelocated section is. This commit includes a fix for that issue by
remembering that pointer, though the longer term fix should be to stop processing
unneeded sections.

Original Summary:

This allows us to get rid of the original unrelocated object file after
we're done processing relocations (but before applying them).
MachO and COFF already do not require this (currently we have temporary hacks
to prevent ownership from being released, but those are brittle and should be
removed soon).

The placeholder mechanism allowed the relocation resolver to look at original
object file to obtain more information that are required to apply the
relocations. This is usually necessary in two cases:

- For relocations targetting sub-word memory locations, there may be pieces
  of the instruction at the target address which we should not override.
- Some relocations on some platforms allow an extra addend to be encoded in
  their immediate fields.

The problem is that in the second case the information cannot be recovered
after the relocations have been applied once because they will have been
overridden. In the first case we also need to be careful to not use any bits
that aren't fixed and may have been overriden by applying a first relocation.

In the past both have been fixed by just looking at original object file. This
patch attempts to recover the information from the first by looking at the
relocated object file, while the extra addend in the second case is read
upon relocation processing and addend to the regular addend.

I have tested this on X86. Other platforms represent my best understanding
of how those relocations should work, but I may have missed something because
I do not have access to those platforms.
We will keep the ugly workarounds in place for a couple of days, so this commit
can be reverted if it breaks the bots.

Differential Revision: http://reviews.llvm.org/D9028

llvm-svn: 236341
2015-05-01 20:21:45 +00:00
Reid Kleckner 2747d3d55a Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
This reverts commit r236339, it breaks the win32 clang-cl self-host.

llvm-svn: 236340
2015-05-01 20:14:04 +00:00
Reid Kleckner 4856fc61b4 [WinEH] Add an EH registration and state insertion pass for 32-bit x86
This pass is responsible for constructing the EH registration object
that gets linked into fs:00, which is all it does in this change. In the
future, it will also insert stores to update the EH state number.

I considered keeping this functionality in WinEHPrepare, but it's pretty
separable and X86 specific. It has conceptually very little to do with
the task of WinEHPrepare, which is currently outlining.  WinEHPrepare is
also in theory useful on ARM, but this logic is pretty x86 specific.

Reviewers: andrew.w.kaylor, majnemer

Differential Revision: http://reviews.llvm.org/D9422

llvm-svn: 236339
2015-05-01 20:04:54 +00:00
Pete Cooper f68d5038e6 [ARM] Transfer the internal flag in thumb2 size reduction.
Converting from t2LDRs to tLDRr caused the shift argument to drop the internal flag.  This would then throw machine verifier errors.

Unfortunately i'm having trouble reducing a test case.  I'm going to keep trying, but so far its a scary combination of machine sinking, an 'and i1', loads feeding loads, and a bunch of code which shouldn't change IT block formation, but does.  Its not useful to commit a test in that state as we have no way of knowing if it even hits this code reliably in future.

rdar://problem/20752113

llvm-svn: 236333
2015-05-01 18:57:32 +00:00
Douglas Katzman e2e72382b9 Move unit test into anonymous namespace as per convention.
llvm-svn: 236332
2015-05-01 18:51:06 +00:00
Alex Lorenz 42e91fa312 YAML: Fix the output of sequences that contain flow sequences.
This patch fixes a bug where the YAML Output class emitted
a sequence of flow sequences without the '-' characters.
Before:
  
  seq:
    [ a, b ]
    [ c, d ]

After:

  seq:
    - [ a, b ]
    - [ c, d ]


Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9206

llvm-svn: 236329
2015-05-01 18:34:25 +00:00
Alex Lorenz 684379a00b Update YamlIO documentation for the ScalarTraits class.
This patch adds the missing context parameter to the
input and output methods in ScalarTraits.

Differential Revision: http://reviews.llvm.org/D9173

llvm-svn: 236328
2015-05-01 18:20:23 +00:00
Peter Collingbourne d27d3a151f ARM: Align functions containing Thumb-2 jump tables to 4 bytes.
Functions with jump tables need an alignment of 4 because they use the ADR
instruction, which aligns the PC to 4 bytes before adding an offset.

Differential Revision: http://reviews.llvm.org/D9424

llvm-svn: 236327
2015-05-01 18:05:59 +00:00
Diego Novillo a7b5c5b584 Fix infinite recursion in ScaledNumber::toInt.
Patch from dexonsmith. The call to toInt() was calling compareTo() which
in some cases would call back to toInt(), creating an infinite loop.

Fixed by simplifying the logic in compareTo() to avoid the co-recursion.

llvm-svn: 236326
2015-05-01 17:59:15 +00:00
James Y Knight 35e04e84fa [Sparc] Repair fixups in little endian mode.
Differential Revision: http://reviews.llvm.org/D9434

llvm-svn: 236324
2015-05-01 17:13:02 +00:00
Douglas Katzman 49e96132ce Fix omission from adding sparcel (original http://reviews.llvm.org/D9263)
"obviously" it needs to go in parseArch *and* getArchTypeForLLVMName.

Differential Revision: http://reviews.llvm.org/D9436

llvm-svn: 236322
2015-05-01 16:49:58 +00:00
Benjamin Kramer 5de990ebca Remove std::move on return of temporary.
No functionality change. Found by -Wpessimizing-move.

llvm-svn: 236318
2015-05-01 15:26:22 +00:00
Benjamin Kramer d5a0b345bb Remove std::move on return of temporary.
No functionality change. Found by -Wpessimizing-move.

llvm-svn: 236317
2015-05-01 15:25:29 +00:00
Benjamin Kramer 548e8a405c Remove std::move on return when it could prevent copy elision.
Found by -Wpessimizing-move, no functional change. The APFloat and
PassManager change doesn't affect codegen as returning a by-value
argument will always result in a move.

llvm-svn: 236316
2015-05-01 15:16:11 +00:00
Toma Tabacu 00e9867988 [mips] [IAS] Fix error messages for using LI with 64-bit immediates.
Summary:
LI should never accept immediates larger than 32 bits.
The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9289

llvm-svn: 236313
2015-05-01 12:19:27 +00:00
Niels Ole Salscheider b0e3c348ab [CMake] Also search for prefixed versions of ld.gold
llvm-svn: 236312
2015-05-01 11:58:30 +00:00
Toma Tabacu a2861db834 [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.
Summary:
Generate one DSLL32 of 0 instead of two consecutive DSLL of 16.
In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned.

This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases.
It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8974

llvm-svn: 236311
2015-05-01 10:26:47 +00:00