f1aab4502e
Delete all of the CodeGenInstructions from CodeGenTarget destructor.
...
llvm-svn: 200906
2014-02-06 06:27:59 +00:00
bc9486bea0
Shrink the size of CodeGenInstruction a little bit by using bitfields. 32 bools seemed excessive.
...
llvm-svn: 200829
2014-02-05 09:10:40 +00:00
4c6129af32
Get rid of a vector copy by just making a pointer out of the reference returned by getInstructionsByEnumValue instead of assigning it to a new vector.
...
llvm-svn: 200828
2014-02-05 07:56:49 +00:00
65efcb4685
Fix a vector that was passed by value instead of reference.
...
llvm-svn: 200827
2014-02-05 07:27:49 +00:00
1129d452cd
Fix a doxygen comment referencing the wrong method name.
...
llvm-svn: 200825
2014-02-05 07:21:07 +00:00
7ca1d18055
Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes from X86 matcher table.
...
llvm-svn: 200821
2014-02-05 05:44:28 +00:00
d8dd194f03
TableGen/X86RecognizableInstr.h: Prune out-of-date "@param isSSE". [-Wdocumentation]
...
llvm-svn: 200628
2014-02-02 10:53:36 +00:00
fa6298a162
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
...
llvm-svn: 200626
2014-02-02 09:25:09 +00:00
8e92e85ac7
Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix.
...
llvm-svn: 200625
2014-02-02 07:46:05 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
...
llvm-svn: 200624
2014-02-02 07:08:01 +00:00
10243c8907
Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters.
...
llvm-svn: 200522
2014-01-31 08:47:06 +00:00
ec68866f55
Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch.
...
llvm-svn: 200520
2014-01-31 07:00:55 +00:00
bdf33ca08d
Couple minor formatting fixes to the XXXGenDAGISel.inc files.
...
llvm-svn: 200459
2014-01-30 06:42:52 +00:00
0d16d2dc31
Delete the Matchers stored in the SmallVectors in SwitchOpcodeMatcher/SwitchTypeMatcher.
...
llvm-svn: 200377
2014-01-29 07:06:07 +00:00
3fa98a65e9
Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
...
llvm-svn: 200349
2014-01-28 23:13:18 +00:00
e6c13e4abd
Change MCStreamer EmitInstruction interface to take subtarget info
...
llvm-svn: 200345
2014-01-28 23:12:42 +00:00
74169dcf45
Improve handling of EnforceSmallerThan. Remove all types that are smaller from the larger set not just the smallest type from the smaller set. Ensure 'smaller' vectors have the same or fewer total bits. Similar for 'larger' vectors.
...
llvm-svn: 200287
2014-01-28 04:49:01 +00:00
6e1faaf886
Don't use EnforceSmallerThan for EnforceVectorSubVectorTypeIs. EnforceSmallerThan doesn't handle vectors quite right and should really enforce that vectors have the same number of elements. Add explicit checks for vector element count differing in EnforceVectorSubVectorTypeIs instead. This removes some unnecessary type checks in X86GenDAGISel.inc.
...
llvm-svn: 200091
2014-01-25 17:40:33 +00:00
336e1f1179
Fix typo in commment tyep->type.
...
llvm-svn: 200089
2014-01-25 17:34:23 +00:00
5f730e8ef1
Use isConcrete and getConcrete instead of using TypeVec directly.
...
llvm-svn: 200071
2014-01-25 05:33:48 +00:00
6dbcb945a2
Fix EnforceSmallerThan to check !hasVectorTypes on the other type instead of this type to force this type to be scalar.
...
llvm-svn: 200070
2014-01-25 05:17:38 +00:00
3f9978e65a
Remove TGValueTypes.cpp from CMakeLists.txt which I forgot to do in r200036.
...
llvm-svn: 200037
2014-01-24 20:51:32 +00:00
8561de90d7
Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).
...
llvm-svn: 200036
2014-01-24 20:50:47 +00:00
cb40291100
Fix known typos
...
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
llvm-svn: 200018
2014-01-24 17:20:08 +00:00
9bbf7ca13d
]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)
...
llvm-svn: 199806
2014-01-22 15:08:36 +00:00
b33c2ef215
[x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
...
llvm-svn: 199804
2014-01-22 15:08:21 +00:00
2ef8d9c05c
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
...
llvm-svn: 199803
2014-01-22 15:08:08 +00:00
a2c60197bf
Use ArrayRef to simplify some code.
...
llvm-svn: 199712
2014-01-21 07:20:05 +00:00
caaa2850c0
[x86] Fix disassembly of MOV16ao16 et al.
...
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.
llvm-svn: 199654
2014-01-20 12:02:53 +00:00
35da3d190a
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
...
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
317e2c499d
replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h>
...
llvm-svn: 199303
2014-01-15 07:59:37 +00:00
b7c7f38918
Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions.
...
llvm-svn: 199295
2014-01-15 05:02:02 +00:00
06234ec147
Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
...
promotion code, Tablegen will now select FPExt for floating point promotions
(previously it had returned AExt, which is not valid for floating point types).
Any out-of-tree targets that were relying on AExt being returned for FP
promotions will need to update their code check for FPExt instead.
llvm-svn: 199252
2014-01-14 19:56:36 +00:00
ad60708a72
Remove stray comma in enum to satisfy -Wpedantic.
...
llvm-svn: 199194
2014-01-14 08:07:10 +00:00
ae11aed9d7
Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
...
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.
llvm-svn: 199193
2014-01-14 07:41:20 +00:00
b19c9dc1a1
AVX-512: Embedded Rounding Control - encoding and printing
...
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.
llvm-svn: 199102
2014-01-13 12:55:03 +00:00
9dc6df5744
Constant propagate MachineInstrClassName.
...
llvm-svn: 198969
2014-01-10 22:59:49 +00:00
f581314932
All backends use MC now.
...
llvm-svn: 198959
2014-01-10 21:49:27 +00:00
a6afef7a51
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off
...
llvm-svn: 198922
2014-01-10 08:05:42 +00:00
2a2a354ee9
Revert "Disable LeakSanitizer in TableGen binaries, see PR18325"
...
To declare or define reserved identifers is undefined behaviour in standard
C++. This needs to be addressed in compiler-rt before it can be used in LLVM.
See the list discussion for details.
This reverts commit r198858.
llvm-svn: 198884
2014-01-09 19:40:55 +00:00
bc60254543
Disable LeakSanitizer in TableGen binaries, see PR18325
...
llvm-svn: 198858
2014-01-09 09:26:26 +00:00
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
...
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
2ea87dad77
The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used.
...
llvm-svn: 198589
2014-01-06 06:57:27 +00:00
d9e1669d1c
Use patterns to remove some duplicate instructions.
...
llvm-svn: 198550
2014-01-05 06:55:48 +00:00
34db6523f3
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
...
llvm-svn: 198547
2014-01-05 05:46:38 +00:00
c0107977d9
Remove no longer needed x86 disassembler hack.
...
llvm-svn: 198546
2014-01-05 05:10:07 +00:00
0550ce7ac1
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
...
llvm-svn: 198545
2014-01-05 04:55:55 +00:00
5165cf78b0
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
...
llvm-svn: 198544
2014-01-05 04:32:42 +00:00
3484fc2161
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
...
llvm-svn: 198543
2014-01-05 04:17:28 +00:00
5999d47538
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
...
llvm-svn: 198530
2014-01-05 01:35:51 +00:00
7d4e01cdcb
Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time.
...
llvm-svn: 198529
2014-01-05 01:34:12 +00:00
bc281ad8c1
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
...
llvm-svn: 198515
2014-01-04 22:29:41 +00:00
1da8582322
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
...
llvm-svn: 198475
2014-01-04 05:09:27 +00:00
49f1c2a733
[TableGen] Handle ValueType in CodeGenDAGPatterns GetNumNodeResults
...
A ValueType in a pattern dag is a type cast, and GetNumNodeResults should
handle it (the type cast has only one result).
This comes up, for example, during the type checking of pattern fragments, for
example, AArch64's Neon_combine_2d fragment is:
dag Operands = (ops node:$Rm, node:$Rn);
dag Fragment = (v2f64 (concat_vectors (v1f64 node:$Rm), (v1f64 node:$Rn)));
llvm-svn: 198347
2014-01-02 20:47:05 +00:00
66c20f344e
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
...
llvm-svn: 198336
2014-01-02 19:12:10 +00:00
fae226c67e
Remove unused HasFROperands field from disassembler.
...
llvm-svn: 198332
2014-01-02 18:44:21 +00:00
eabdbcb8a9
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
...
llvm-svn: 198327
2014-01-02 18:20:48 +00:00
a941d2b08e
Remove unnecessary stirng comparison from disassembler.
...
llvm-svn: 198325
2014-01-02 17:41:40 +00:00
9dd48c8ed4
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
...
llvm-svn: 198323
2014-01-02 17:28:14 +00:00
83b7e24b76
Remove unused function argument.
...
llvm-svn: 198291
2014-01-02 03:58:45 +00:00
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
...
llvm-svn: 198284
2014-01-01 21:52:57 +00:00
9155118602
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
...
llvm-svn: 198278
2014-01-01 15:29:32 +00:00
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
...
Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
623b0d64b3
Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
...
llvm-svn: 198276
2014-01-01 14:22:37 +00:00
e98c8cb9f0
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
...
llvm-svn: 198265
2013-12-31 17:21:44 +00:00
0e21bca6dd
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
...
llvm-svn: 198238
2013-12-30 19:16:48 +00:00
6d776e2660
Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change.
...
llvm-svn: 198226
2013-12-30 17:37:10 +00:00
afad4dc633
Simplify filter accepts function to just return 'condition' instead of branching to return true/false. No functional change.
...
llvm-svn: 198221
2013-12-30 17:22:20 +00:00
371e363833
AVX-512: decoder for AVX-512, made by Alexey Bader.
...
llvm-svn: 198013
2013-12-25 11:40:51 +00:00
c0a5aaeab0
[x86] Rename In32BitMode predicate to Not64BitMode
...
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)
Patch by David Woodhouse
llvm-svn: 197768
2013-12-20 02:04:49 +00:00
71b2e20df9
Add support for positionally-encoded operands to FixedLenDecoderEmitter
...
Unfortunately, the PowerPC instruction definitions make heavy use of the
positional operand encoding heuristic to map operands onto bitfield variables
in the instruction definitions. Changing this to use name-based mapping is not
trivial, however, because additional infrastructure needs to be designed to
handle mapping of complex operands (with multiple suboperands) onto multiple
bitfield variables.
In the mean time, this adds support for positionally encoded operands to
FixedLenDecoderEmitter, so that we can generate a disassembler for the PowerPC
backend. To prevent an accidental reliance on this feature, and to prevent an
undesirable interaction with existing disassemblers, a backend must opt-in to
this support by setting the new decodePositionallyEncodedOperands
instruction-set bit to true.
When enabled, this iterates the variables that contribute to the instruction
encoding, just as the encoder does, and emulates the procedure the encoder uses
to map "numbered" operands to variables. The bit range for each variable is
also determined as the encoder determines them. This map is then consulted
during the decoder-generator's loop over operands to decode, allowing the
decoder to understand both position-based and name-based operand-to-variable
mappings.
As noted in the comment on the decodePositionallyEncodedOperands definition,
this support should be removed once it is no longer needed. There should be no
change to existing disassemblers.
llvm-svn: 197691
2013-12-19 16:12:53 +00:00
9d95e8d530
Add support for PointerLikeRegClass to FixedLenDecoderEmitter
...
This is more prep for adding the PowerPC disassembler. FixedLenDecoderEmitter
should recognize PointerLikeRegClass operands as register types, and generate
register-like decoding calls instead of treating them like immediates.
llvm-svn: 197680
2013-12-19 14:58:22 +00:00
81e6fccbd7
Support little-endian encodings in the FixedLenDecoderEmitter
...
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.
This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).
llvm-svn: 197532
2013-12-17 22:37:50 +00:00
47fc44e52e
AVX-512: Added legal type MVT::i1 and VK1 register for it.
...
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
llvm-svn: 197384
2013-12-16 13:52:35 +00:00
f907b891da
Correct word hyphenations
...
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.
llvm-svn: 196471
2013-12-05 05:44:44 +00:00
53c2b1ea59
Remove dead code.
...
llvm-svn: 196066
2013-12-02 05:10:04 +00:00
05c5a93283
[weak vtables] Place class definitions into anonymous namespaces to prevent weak vtables.
...
This patch places class definitions in implementation files into anonymous
namespaces to prevent weak vtables. This eliminates the need of providing an
out-of-line definition to pin the vtable explicitly to the file.
llvm-svn: 195092
2013-11-19 03:08:35 +00:00
d12ccbd343
[weak vtables] Remove a bunch of weak vtables
...
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
llvm-svn: 195064
2013-11-19 00:57:56 +00:00
49109a279c
Revert r194865 and r194874.
...
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
llvm-svn: 194997
2013-11-18 09:31:53 +00:00
31377593bc
TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.
...
llvm-svn: 194978
2013-11-17 21:24:41 +00:00
b88cc2fc52
Small improvement to InstrinsicEmitter::EmitAttributes. This change removes the “pushing” and “clearing” of the SmallVector and instead uses const arrays to pass the attributeKinds to AttributeSet::get .
...
Patch by Aditya Nandakumar.
llvm-svn: 194899
2013-11-16 00:20:01 +00:00
dbedae89b9
[weak vtables] Remove a bunch of weak vtables
...
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
llvm-svn: 194865
2013-11-15 22:34:48 +00:00
dacddb0bab
AVX-512: added VPCONFLICT instruction and intrinsics,
...
added EVEX_KZ to tablegen
llvm-svn: 193959
2013-11-03 13:46:31 +00:00
74f4c749cf
Lower stackmap intrinsics directly to their target opcode in the DAG builder.
...
llvm-svn: 193769
2013-10-31 17:18:24 +00:00
a2efd99bdf
Enable variable arguments support for intrinsics.
...
llvm-svn: 193766
2013-10-31 17:18:11 +00:00
d4d1d9c06e
whitespace
...
llvm-svn: 193765
2013-10-31 17:18:07 +00:00
a70ecdc3ac
TableGen: remove unused variable.
...
llvm-svn: 193527
2013-10-28 18:19:04 +00:00
141075110c
TableGen: Refactor DAG patterns to enable parsing one pattern at a time.
...
llvm-svn: 193526
2013-10-28 18:07:21 +00:00
bd2140018b
TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.
...
These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.
llvm-svn: 193525
2013-10-28 18:07:17 +00:00
a5906f06aa
Typo.
...
llvm-svn: 193043
2013-10-20 03:19:25 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
...
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
88adf2a49c
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
...
llvm-svn: 192525
2013-10-12 05:41:08 +00:00
aab53e7785
Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
...
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
981af0021b
Add missing #include's to cctype when using isdigit/alpha/etc.
...
llvm-svn: 192519
2013-10-12 00:55:57 +00:00
81034928c6
Remove another unnecessary filter from the disassembler.
...
llvm-svn: 192425
2013-10-11 06:59:57 +00:00
e1ceeb40c1
Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
...
llvm-svn: 192339
2013-10-10 04:26:52 +00:00
2d0d180ab4
More x86 disassembler filtering cleanup.
...
llvm-svn: 192279
2013-10-09 06:12:53 +00:00
043d749ba3
Remove some old filters from the x86 disassembler table builder.
...
llvm-svn: 192275
2013-10-09 05:02:29 +00:00
a984729f8a
Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
...
llvm-svn: 192175
2013-10-08 06:30:39 +00:00
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
...
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Craig Topper