Commit Graph

102264 Commits

Author SHA1 Message Date
Tim Northover 3ec1de7767 AArch64/ARM64: port across stub handling for ELF C++ exceptions.
The most important part here is that we should actuall emit the stubs we refer
to in the exception table, but as a side issue this uses more sensible & GCC
compatible representations for some of the bits of information.

llvm-svn: 206380
2014-04-16 11:52:55 +00:00
Tim Northover 18f68f6d1a ARM64: use 32-bit moves for constants where possible.
If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.

Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.

llvm-svn: 206379
2014-04-16 11:52:51 +00:00
Tim Northover 9cfb57dafa ARM64: use the integrated assembler on ELF.
llvm-svn: 206378
2014-04-16 11:52:40 +00:00
Matheus Almeida dc7e48e084 [mips] Emit '.set nomicromips' before a function's entry label
if not in micromips mode.

The test (elf_st_other.ll) was renamed as the name and description didn't
make sense as the test wasn't checking any symbol table entry.

Differential Revision: http://reviews.llvm.org/D3346

llvm-svn: 206377
2014-04-16 11:46:59 +00:00
Aaron Ballman 58ce7f24cd Fixing a compile error in debug versions of MSVC. It seems that the range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used.
llvm-svn: 206376
2014-04-16 11:15:57 +00:00
Chandler Carruth eacd996daf [LCG] Stop playing fast and loose with reference members and assignment.
It doesn't work. I'm still cleaning up all the places where I blindly
followed this pattern. There are more to come in this code too.

As a benefit, this lets the default copy and move operations Just Work.

llvm-svn: 206375
2014-04-16 11:14:28 +00:00
Chandler Carruth 0e31ed9058 [Allocator] Make BumpPtrAllocator movable and move assignable.
llvm-svn: 206372
2014-04-16 10:48:27 +00:00
Daniel Sanders 11c0c067c2 [mips] Correct callee saved list for the N32 ABI and enable test
Summary: Depends on D3339

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3340

llvm-svn: 206371
2014-04-16 10:23:37 +00:00
Daniel Sanders 9fe0ad0c07 [mips] Add calling convention tests covering O32, N32, and N64.
Summary:
I had difficulty finding tests for the N32 and N64 ABI so I've added a
collection of calling convention tests based on the document MIPS ABIs
Described (MD00305), the MIPSpro N32 Handbook, and the SYSV ABI. Where the
documents/implementations disagree, I've used GCC to resolve the conflict.

A few interesting details:
* For N32, LLVM uses 64-bit pointers when saving $ra despite pointers being
  32-bit. I've yet to find a supporting statement in the ABI documentation but
  the current behaviour matches GCC.

* For O32, the non-variable portion of a varargs argument list is also subject
  to the rule that floating-point is passed via GPR's (on N32/N64 only the
  variable portion is subject to this rule). This agrees with GCC's behaviour
  and the SYSV ABI but contradicts part of the MIPSpro N32 Handbook which talks about O32's behaviour.

* The N32 implementation has the wrong callee-saved register list.
  (I already have a fix for this but will commit it as a follow-up).

I've left RUN-TODO lines in for O32 on MIPS64. I don't plan to support this case
for now but we should revisit it.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3339

llvm-svn: 206370
2014-04-16 09:59:46 +00:00
Chandler Carruth 448ce011ab [Allocator] Nuke to useless functions. The implicit ones are sufficient
here (obviously).

llvm-svn: 206369
2014-04-16 09:21:29 +00:00
Tim Northover f8d183e8b9 ARM64: explicitly ask for Apple NEON syntax so test passes on Linux
llvm-svn: 206368
2014-04-16 09:13:44 +00:00
Tim Northover 97c5b6fe4f ARM64: mark x7 as used when an i128 gets shunted onto the stack.
The second half of a split i128 was ending up in x7, which is not a good thing.

This is another part of PR19432.

llvm-svn: 206366
2014-04-16 09:03:25 +00:00
Tim Northover 863a789a99 DAGCombiner: don't optimise non-existant litpool load
This particular DAG combine is designed to kick in when both ConstantFPs will
end up being loaded via a litpool, however those nodes have a semi-legal
status, dictated by isFPImmLegal so in some cases there wouldn't have been a
litpool in the first place. Don't try to be clever in those circumstances.

Picked up while merging some AArch64 tests.

llvm-svn: 206365
2014-04-16 09:03:09 +00:00
Timur Iskhodzhanov 42b1b517ce Simplify a static_assert so VS2013 can build it
llvm-svn: 206363
2014-04-16 08:30:32 +00:00
Saleem Abdulrasool 057094c6f6 COFF: fix an off by one error
Adjust the tests to validate the number of auxiliary entries used to store the
filename.

Thanks to majnemer's sharp eye for catching the missing - 1 in the round up
calculation.

llvm-svn: 206359
2014-04-16 06:22:53 +00:00
Craig Topper abb4ac7f87 Convert SelectionDAG::getVTList to use ArrayRef
llvm-svn: 206357
2014-04-16 06:10:51 +00:00
Craig Topper ada0857679 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.
llvm-svn: 206356
2014-04-16 04:21:27 +00:00
Saleem Abdulrasool a2bf05aa2f COFF: add support for .file symbols
Add support for emitting .file records.  This is mostly a quality of
implementation change (more complete support for COFF file emission) that was
noticed while working on COFF file emission for Windows on ARM.

A .file record is emitted as a symbol with storage class FILE (103) and the name
".file".  A series of auxiliary format 4 records follow which contain the file
name.  The filename is stored as an ANSI string and is padded with NULL if the
length is not a multiple of COFF::SymbolSize (18).

llvm-svn: 206355
2014-04-16 04:15:32 +00:00
Saleem Abdulrasool 3b5e00130e tools: fix invalid printing, buffer overrun in llvm-readobj
All auxiliary records are consumed when accessing a File record.

llvm-svn: 206354
2014-04-16 04:15:29 +00:00
Saleem Abdulrasool 0d3d6c45ef Target: whitespace
llvm-svn: 206353
2014-04-16 04:15:25 +00:00
Matt Arsenault 4ef2588b65 R600: Extend r600 sign_extend_inreg tests for EG
Patch by: Jan Vesely <jan.vesely@rutgers.edu>

llvm-svn: 206349
2014-04-16 01:41:34 +00:00
Matt Arsenault 4e46665a80 R600: Expand sign extension of vectors.
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.

v2: move setOperation() calls to R600ISelLowering.cpp.
    cleanup the SI code to make it obvious that this patch does is nop for SI

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

llvm-svn: 206348
2014-04-16 01:41:30 +00:00
Jim Grosbach 36c6a50512 [ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.
No functional change.

llvm-svn: 206344
2014-04-16 00:42:46 +00:00
Jim Grosbach 01fc5887ad ARM64: Nuke some dead code.
Missed in previous commit.

llvm-svn: 206343
2014-04-16 00:42:43 +00:00
Jim Grosbach 80633094f8 [ARM64,C++11] Clean up the ARM64 LOH collection pass.
Range'ify a bunch of loops, mainly. As a result, we have a variety
of objects via reference rather than by pointer, so propogate that
through the various helper functions where it makes sense.

llvm-svn: 206337
2014-04-15 22:57:02 +00:00
Matt Arsenault e500e32939 R600/SI: Print code size along with used registers
llvm-svn: 206336
2014-04-15 22:40:47 +00:00
Matt Arsenault 4d7d38333b R600/SI: Print more immediates in hex format
Print in decimal for inline immediates, and hex otherwise. Use hex
always for offsets in addressing offsets.

This approximately matches what the shader compiler does.

llvm-svn: 206335
2014-04-15 22:32:49 +00:00
Matt Arsenault fcf86c5417 R600/SI: Cleanup parsing of register names.
Try to figure out the class and number of subregisters.

llvm-svn: 206334
2014-04-15 22:32:42 +00:00
Nick Lewycky 43855af9a7 Make this test not match its own filename, when being run from a path that includes the string 'add'.
llvm-svn: 206331
2014-04-15 22:29:32 +00:00
Matt Arsenault 470acd81a8 R600/SI: Fix loads of i1
llvm-svn: 206330
2014-04-15 22:28:39 +00:00
Tobias Grosser 8d941ef30d RegionInfo: Do not access a value that was just moved away
This fixes a regression introduced in r206310.

llvm-svn: 206328
2014-04-15 22:09:36 +00:00
Chandler Carruth a073f253f3 [Allocator] Fold the two templated overloads into a single one with
a default argument. The allocator interface we're modeling doesn't
distinguish between array and non-array allocation.

llvm-svn: 206327
2014-04-15 21:51:14 +00:00
Chandler Carruth 9c2a3958f0 [Allocator] Remove a really problematic overload. This is very confusing
because there is another (size_t, size_t) overload of Allocator, and the
only distinguishing factor is that one is a tempalte and the other
isn't. There was only one usage of this and that one was easily
converted to carry the alignment constraint in the type itself.

llvm-svn: 206325
2014-04-15 21:36:02 +00:00
Akira Hatanaka 3d90f99d1a Make FastISel::SelectInstruction return before target specific fast-isel code
handles Intrinsic::trap if TargetOptions::TrapFuncName is set.

This fixes a bug in which the trap function was not taken into consideration
when a program was compiled without optimization (at -O0).

<rdar://problem/16291933>

llvm-svn: 206323
2014-04-15 21:30:06 +00:00
Andrea Di Biagio aac2eac4c2 [X86] Improve the lowering of packed shifts by constant build_vector.
This patch teaches the backend how to efficiently lower logical and
arithmetic packed shifts on both SSE and AVX/AVX2 machines.

When possible, instead of scalarizing a vector shift, the backend should try
to expand the shift into a sequence of two packed shifts by immedate count
followed by a MOVSS/MOVSD.

Example
  (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))

Can be rewritten as:
  (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))

[with X and Y ConstantInt]

The advantage is that the two new shifts from the example would be lowered into
X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into
four scalar shifts plus four pairs of vector insert/extract.

llvm-svn: 206316
2014-04-15 19:30:48 +00:00
Quentin Colombet 72dad56c53 [ARM64] Set default CPU to generic instead of cyclone.
llvm-svn: 206313
2014-04-15 19:08:46 +00:00
Robert Lougher a9bf2463b9 Revert r191049/r191059 as it can produce wrong code (see PR17975).
It has already been reverted on the 3.4 branch in r196521.

llvm-svn: 206311
2014-04-15 18:34:24 +00:00
David Blaikie ec649acb82 Use unique_ptr to manage ownership of child Regions within llvm::Region
llvm-svn: 206310
2014-04-15 18:32:43 +00:00
Julien Lerouge be4fe32eb8 Add lifetime markers for allocas created to hold byval arguments, make them
appear in the InlineFunctionInfo.

llvm-svn: 206308
2014-04-15 18:06:46 +00:00
Julien Lerouge 957e91c4d8 Split byval argument initialization so the memcpy(s) are injected at the
beginning of the first new block after inlining.

llvm-svn: 206307
2014-04-15 18:01:54 +00:00
Duncan P. N. Exon Smith 2b69189c9c LTO: Add more loop simplification passes to LTO
Similar to r202051, add missing loop simplification passes to the LTO
optimization pipeline.

Patch by Rafael Espindola.

llvm-svn: 206306
2014-04-15 17:48:15 +00:00
Duncan P. N. Exon Smith 0d640014ff verify-di: Add back braces for MSVC compatability
Fixup after r206300.

<rdar://problem/15500563>

llvm-svn: 206305
2014-04-15 17:28:26 +00:00
Duncan P. N. Exon Smith 6ef5f284d6 verify-di: Implement DebugInfoVerifier
Implement DebugInfoVerifier, which steals verification relying on
DebugInfoFinder from Verifier.

  - Adds LegacyDebugInfoVerifierPassPass, a ModulePass which wraps
    DebugInfoVerifier.  Uses -verify-di command-line flag.

  - Change verifyModule() to invoke DebugInfoVerifier as well as
    Verifier.

  - Add a call to createDebugInfoVerifierPass() wherever there was a
    call to createVerifierPass().

This implementation as a module pass should sidestep efficiency issues,
allowing us to turn debug info verification back on.

<rdar://problem/15500563>

llvm-svn: 206300
2014-04-15 16:27:38 +00:00
Duncan P. N. Exon Smith 67b44da0dd verify-di: split out VerifierSupport
Split out assertion and output helpers from Verifier in preparation for
writing the DebugInfoVerifier.

<rdar://problem/15500563>

llvm-svn: 206299
2014-04-15 16:27:32 +00:00
David Blaikie 0afad5e8bc Use unique_ptr to manage PassInfo instances in the PassRegistry
llvm-svn: 206297
2014-04-15 15:17:14 +00:00
NAKAMURA Takumi e1f3583b96 MipsAsmParser.cpp: Fix vg_leak in MipsOperand::CreateMem(). Mem.Base is managed by k_Memory itself.
llvm-svn: 206293
2014-04-15 14:13:21 +00:00
NAKAMURA Takumi bd524ef129 MipsAsmParser::ParseRegister(): Be responsible to delete an Operand on a temporary Operands.
llvm-svn: 206292
2014-04-15 14:06:27 +00:00
Tim Northover bd668872c0 AArch64/ARM64: enable more AArch64 tests on ARM64.
No code changes for this bunch, just some test rejigs.

llvm-svn: 206291
2014-04-15 14:00:29 +00:00
Tim Northover ebb3123a5f AArch64/ARM64: add missing pattern for extending load.
llvm-svn: 206290
2014-04-15 14:00:19 +00:00
Tim Northover cbcb7a37f7 AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.

llvm-svn: 206289
2014-04-15 14:00:15 +00:00