llvm-project

Author	SHA1	Message	Date
QingShan Zhang	2133d3c558	[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal' For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG. Differential Revision: https://reviews.llvm.org/D70000	2020-01-03 03:26:41 +00:00
QingShan Zhang	add7f2aba7	[NFC] Add one test to verify the sign_extend of vector type.	2019-11-11 09:44:13 +00:00

Author

SHA1

Message

Date

QingShan Zhang

2133d3c558

[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

For now, we didn't set the default operation action for SIGN_EXTEND_INREG for
vector type, which is 0 by default, that is legal. However, most target didn't
have native instructions to support this opcode. It should be set as expand by
default, as what we did for ANY_EXTEND_VECTOR_INREG.

Differential Revision: https://reviews.llvm.org/D70000

2020-01-03 03:26:41 +00:00

QingShan Zhang

add7f2aba7

[NFC] Add one test to verify the sign_extend of vector type.

2019-11-11 09:44:13 +00:00

2 Commits